Abstract: An asynchronous transfer mode switch with shared memory under the control of a content addressable memory, receives serially through a plurality of input ports a plurality of cells of digital data packets during a specific time period, each packet having a header. The header of each said cell is processed and temporarily stored. The data bits of each cell are temporarily stored, and transferred in parallel to a random access memory, using available addresses in said random access memory. A header processor assigns an arrival number to each received cell, and extracts the output port destination and priority of each cell from said headers. A content addressable memory stores the arrival number, output destination port and priority of each data cell. A read control provides sequentially, in order of priority, arrival numbers, and destination addresses, to said content addressable memory for determining the order in which cells of data are read from said random access memory.

Abstract: A broadband space switch matrix includes a parallel combination of individual switch modules each comprising a cascade of pass-transistor selectors, NAND gates, and inverters arranged into a multi-stage tree multiplexing configuration. The switching speed is increased by isolating each switching crosspoint from the stray capacitive loading in the matrix.

Abstract: A broadband space switch matrix constructed from a plurality of NAND gates arranged into a set of cascaded stages to form a tree-switch multiplexing configuration. A plurality of input digital signals are applied to input ports coupled to the NAND gates in the first stage. A selected one of the input signals emerges as an output signal from an output port coupled to a single NAND gate in the last stage. Each NAND gate has a select line for receiving control signals. The switching path for the selected input signal is established by placing the sequence of NAND gates defined by the selected switching path in a state of conduction whereby only the selected input signal propagates through the switch. This is effected by forcing to a HIGH state the particular NAND gates in each stage whose outputs are coupled to the same NAND gate in the following stage along with the output of the NAND gate in the current stage which is in the chosen path.

Abstract: A broadband space tree-switch matrix establishes a desired switching path by sensitizing only the sequence of logic gates defined by the desired path such that only these sensitized logic gates are operable to undergo switching and thereby permit transmission of only the corresponding input signal. The tree-switch includes a plurality of cascaded stages wherein the first stage consists of dual-input NAND gates each receiving a corresponding input signal at one input and a control signal at another input. The remaining stages include a plurality of switching nodes each having a first NAND gate cascaded to a second NAND gate wherein the second NAND gate has a HIGH steady-state logic signal present at one of its inputs. An appropriate combination of control signals are applied to the NAND gates in the first stage to effect a selected switching path. A second broadband space switch matrix comprises a plurality of NAND gates arranged into a series of cascaded stages to form a tree-switch configuration.

Abstract: A broadband switching matrix having M.times.N crosspoint switches is arranged into a selected number of groups of vertically cascaded stages in which adjacent groups are interconnected with expansion stages. An input signal switched from row to column in a particular group propagates through the remaining stages in that group and then propagates successively through the expansion stages in each following group before reaching an output port. In another array configuration, a set of N multiplexers arranged in parallel each receive N input signals and provide a single output signal at a respective output port. The multiplexers are constructed from 2:1 selector elements which are arranged in a vertical tree configuration having log.sub.2 N cascaded stages. Each multiplexer has the same number of stages and hence selector elements. Both broadband switching arrays are designed so that each switch drives only one other switch in the array, thereby minimizing capacitive loading and maximizing propagation speed.

Abstract: A broadband switching array for equalizing the delay experienced by input signals as they propagate through their respective swtiching hpaths, and for providing output signals having uniform logical polarities. A cascaded set of delay means is connected to each of the input ports of the array in accordance with the amount of additional delay that is needed to accomplish equalization. Likewise, a cascaded set of inverter means is connected to each ouput port so that each switching path performs a common number of inversion operations, thereby allowing the output signals to have the same logical polarity.

Abstract: A system for transmitting digital signals over a transmission line including a driver of an inverter employing CMOS FET's and a termination of an inverter employing CMOS FET's. A sense/control circuit at the termination senses changes in the operating condition of the driver inverter and in response thereto controls the operating condition of the termination inverter. Under steady state conditions the termination inverter establishes the appropriate voltage at an output connection coupled thereto without dissipating any power.

Abstract: A crosspoint switching array of a matrix of crosspoint switches connected in rows and columns. Each crosspoint switch includes an MOS inverter circuit for propagating a digital signal from crosspoint-to-crosspoint along its row. Each crosspoint switch includes a first MOS switch connected to the preceding crosspoint switch in the column and a second MOS switch connected to its row. The second switch is activated to connect the row to the column at a particular crosspoint. Otherwise, the first switch is activated to connect the crosspoint switch to the preceding crosspoint switch in the column. The output of the first or second switch is applied to an MOS inverter circuit for driving the following crosspoint switch in the column.

Abstract: In a digital communication system including a central PABX subsystem coupled by a transmission line to a remote telephone subsystem, a method for establishing synchronization between the PABX and the telephone. The data format includes a message transmitted from the PABX to the telephone during the first half of a frame and a response transmitted from the telephone to the PABX during the second half of the frame. The synchronization method includes the steps of recognizing that synchronization has been lost, discontinuing transmission of responses by placing the line driver in a high impedance state while continuing transmission of messages, and detecting a valid message on the transmission line. The valid message is detected by finding in sequence, a message stop bit, the stop bit remaining on the line for one half frame and a message start bit. When a valid message is detected, transmission of responses is resumed.

Abstract: In a data transmission system including a central subsystem coupled by transmission lines of different lengths to a plurality of remote subsystems, methods and apparatus for synchronizing responses to messages transmitted by the central subsystem to compensate for different line delays are provided. The messages are transmitted by the central subsystem during the first portion of a frame, while the responses are transmitted by the remote subsystems during a second portion of the frame. In each of the remote subsystems, a compensation delay equal to a maximum line delay associated with the longest of the transmission lines less an actual line delay associated with the transmission line connected to that remote subsystem is determined. The response to the message is then delayed by the compensation delay so that the responses from each remote subsystem arrive at the central subsystem delayed by the maximum time delay.

Abstract: A digital switching system is described for providing time division multiplexed digital communication of parallel sequential signals of N words each of M bit length between N telephone data subscribers over N transmission lines in which an array of orthogonal RAM memory devices provide parallel-to-serial conversion and multiplexing of the N words each of M bit length to provide a time division multiplexed serial digital bit stream of M words, each N bits in length, which are transmitted over a transmission line to a serial-to-parallel converter and coupled to a second orthogonal RAM memory device in which the N words M bits in length from the serial-to-parallel converter are stored and coupled to N telephone data subscribers over the transmission lines.

Abstract: A digital switching system for switching messages between a plurality of subscribers located a relatively short distance from the switching system. The message format for the system comprises the serial transmission of messages of M bits of information which are transmitted from the switching system to the subscribers during one-half of a transmission frame and messages of M bits of information which are transmitted from the subscribers to the switching system during the other half of the transmission format. Addressable memory arrays are employed at the switching system for multiplexing and serial-to-parallel conversion and switching. In a preferred embodiment up to 40 telephone and/or data terminal messages are handled in 125 microsecond time frames with 8 bit voice and 8 bit data words plus a start and stop bit and 1 signalling bit message format from each of the subscribers.

Abstract: A two-wire bidirectional transmission system for transmitting electrical signals simultaneously in opposite directions between terminals over a pair of wires wherein the transmitter at one terminal transmits a voltage signal over one of said wires while the transmitter at the second terminal generates a voltage signal over the same wire, the second wire being grounded at each end. Impedance matching resistors, that is resistors matched to the impedance of the two wires, are coupled between each of the transmitters and the wire upon which the voltage signal is generated. A subtractor circuit is provided at each of the terminals for linearly subtracting a signal proportional to one-half of the voltage transmitted and thereby receiving at each terminal a voltage signal equal to one-half of the voltage transmitted by the opposite terminal.