Abstract: In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of a first functional component is stored to an input memory of a next functional component. Thus when the first functional component completes its processing, its output is ready to be accessed as input to the next functional component. In an embodiment, the memory device further comprises a partition mechanism for simultaneously accepting output writing from the first functional component and accepting input reading from the second functional component. In another embodiment, the present integrated circuit comprises at least two functional components and at least two memory devices, together with a controller for switching the connections between the functional components and the memory devices.

Abstract: The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the influence or input from the processing unit. In an embodiment, the present method chains a plurality of functional blocks together by software so that one functional block starts after the completion of another functional block. The configuration of the chain can be series, parallel, and any combination thereof, arranged to meet the circuit's objective. The chaining can be configured and re-configured, preferably by software input. The chaining can also be performed at design time or at run time. The chaining can also be modified, preferably at design time, but can also be modified at run time.

Abstract: The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof.

Abstract: A data processing apparatus is provided, which is operable to access data values associated with a respective address values. The data processing apparatus has: a processor; a main memory having a secure data values region; a cache; and cache interface logic having data transaction logic and security determination logic. The data transaction logic receives from the processor a data access request for accessing data in cache. The data access request has an associated address value and a security attribute. If the security attribute indicates that the request is a non-secure data-access request, the security determination logic determines, via a data region allocation table, whether the request is associated with the secure data values region of main memory and the non-secure data access request is allowed to complete if it is not associated with the secure data region.

Abstract: Methods and apparatuses for establishing a trusted group of users to prevent undesirable communication by employing authenticated contact information. In an embodiment, the present invention embeds authenticated contact information to data communication composed by members of the trusted group. Authenticated contact information is preferably disposable contact information, changeable as desired, at a regular interval, or one-time contact information. In another embodiment, the present invention discloses a process of expanding an existing trusted group of users to an outsider, comprising embedding authenticated contact information of a member within the trusted group to a data communication composed by the outsider to a member of the trusted group.

Abstract: The present invention relates to a flexible and reconfigurable bus fabric for microelectronic processing units, which can offer efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the present reconfigurable bus fabric comprises a multistate intersection between two data buses. Preferably, the multistate intersection comprises at least two states, a connecting state connecting the two data buses, and a disconnecting state disconnecting the two data buses. The multistate intersection provides a reconfigurable bus fabric, allowing different connection configuration for the data buses. This reconfigurable bus fabric offers soft-configurability and soft-reconfigurability, using software programming to arrange the circuits' interconnections. Other configurations are also disclosed in exemplary embodiments.

Abstract: The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the influence or input from the processing unit. In an embodiment, the present method chains a plurality of functional blocks together by software so that one functional block starts after the completion of another functional block. The configuration of the chain can be series, parallel, and any combination thereof, arranged to meet the circuit's objective. The chaining can be configured and re-configured, preferably by software input. The chaining can also be performed at design time or at run time. The chaining can also be modified, preferably at design time, but can also be modified at run time.

Abstract: In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of a first functional component is stored to an input memory of a next functional component. Thus when the first functional component completes its processing, its output is ready to be accessed as input to the next functional component. In an embodiment, the memory device further comprises a partition mechanism for simultaneously accepting output writing from the first functional component and accepting input reading from the second functional component. In another embodiment, the present integrated circuit comprises at least two functional components and at least two memory devices, together with a controller for switching the connections between the functional components and the memory devices.

Abstract: The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof.

Abstract: The present invention relates to a flexible and reconfigurable bus fabric for microelectronic processing units, which can offer efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the present reconfigurable bus fabric comprises a multistate intersection between two data buses. Preferably, the multistate intersection comprises at least two states, a connecting state connecting the two data buses, and a disconnecting state disconnecting the two data buses. The multistate intersection provides a reconfigurable bus fabric, allowing different connection configuration for the data buses. This reconfigurable bus fabric offers soft-configurability and soft-reconfigurability, using software programming to arrange the circuits' interconnections. Other configurations are also disclosed in exemplary embodiments.

Abstract: A long-acting antiparasitic formulation suitable for topical application including: (a) 0.1-50% w/v an avermectin or milbemycin having activity against endo- and/or ectoparasites; (b) 1-50% v/v a di(C2-4 glycol) mono(C1-4 alkyl) ether; (c) an optional antioxidant; and (d) an optional skin acceptable volatile solvent q.s. v/v.

Abstract: Long-acting antiparasitic formulations of doramectin, suitable for injection, are described herein.

Abstract: Long-acting antiparasitic formulations of doramectin, suitable for injection, are described herein.

Abstract: A long-acting antiparasitic formulation suitable for topical application including:

Abstract: A still camera or motion picture camera wherein the means for monitoring the brightness of a portion of or entire scene transmits signals to an automatic focusing mechanism as well as to the exposure controls. The connection between the output or outputs of the monitoring means and the exposure controls includes elements which can transmit signals denoting the peak value, the integral value or the average value of signals denoting the scene brightness.

Abstract: A still camera or motion picture camera wherein the means for monitoring the brightness of a portion of or entire scene transmits signals to an automatic focusing mechanism as well as to the exposure controls. The connection between the output or outputs of the monitoring means and the exposure controls includes elements which can transmit signals denoting the peak value, the integral value or the average value of signals denoting the scene brightness.

Abstract: A focussing system emits an infrared light beam towards the subject, the reflected beam passing through an infrared filter and being projected by a spot optics as a small spot onto a pair of photosensitive elements. The spot optics shifts in a plane normal to the camera's optical axis in dependence upon rotation of the camera's focussing ring, to vary the distribution of the reflected beam onto the two elements, the distribution being equal between them when the state of focus is correct. A circuit derives, from the output signals of the two photosensitive elements, a state-of-focus signal used to automatically focus or else to indicate to the user the direction in which he should manually adjust focus. When focussing is finished, the photosensitive elements are disconnected from the focussing circuitry and connected to the camera's exposure-control circuitry, to thereby serve a dual function. The infrared filter moves out of the light path of the photosensitive elements.

Abstract: The film is provided with an audio track comprised of recorded sections alternating with unrecorded sections. An adjustable mixer having first and second inputs is connected to the input of the sound-reproducing unit. A first signal-transmission path extends from the output of the audio head for the audio track to the first input of the mixer. A second signal-transmission path extends to the second input of the mixer and transmits a second audio signal thereto. A control head located upstream of the audio head senses the presence or absence of recorded information on the audio track and controls the operation of an attenuator connected in the second signal-transmission path. The control head is connected to the attenuator via a time-delay circuit which introduces a time delay corresponding to the distance between the two heads.

Abstract: The camera has a housing and a lens. A film transport mechanism is arranged in the housing. An operating element includes a member which is displaceable by a user in longitudinal direction of the optical axis of the lens and which, during at least part of such displacement, actuates the film transport mechanism. The operating element may include two of these members; if so, they are located at opposite lateral sides of the lens and are coupled so as to move in unison.

Abstract: An accessory unit, for example an electronic flash unit, for use with photographic apparatus has a housing provided with one or more connecting elements for detachably connecting the unit to the apparatus. The housing has a through-going, essentially slot-shaped passage through which self-developing film sheets ejected from the apparatus can pass, or through which a strap or other retaining element of the camera can extend which holds the unit adjacent to the camera even when the unit is not in operative position, i.e. when the unit is detached from the photographic apparatus.