Abstract: In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing an embodiment of the method comprises a first amplifier stage with an integrator circuit and connected with a second amplifier stage (A2) following the first amplifier stage and with an integrator circuit, and a sampling capacitor connected between an output of the first amplifier stage and an input of the second amplifier stage.

Abstract: A method of operating a passive matrix addressable ferroelectric device having a voltage pulse protocol with a pre-disturb and post-disturb cycle before and after a disturb generating operation cycle respectively in order to minimize the effect of disturb voltage on non-addressed memory cells, when such voltages are generated thereto in the operation cycle when It is applied for either a write or read operation.

Abstract: In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing the method of the invention comprises a first amplifier stage (A1) with an integrator circuit (715) and connected with a second amplifier stage (A2) following the first amplifier stage and with an integrator circuit (725), and a sampling capacitor (720) connected between an output (716) of the first amplifier stage (A1) and an input (722) of the second amplifier stage (A2).

Abstract: A memory constructed from a dielectric layer sandwiched between a plurality of word conductors and a plurality of bit line conductors is disclosed. The dielectric layer includes a layer of ferroelectric material, and has first and second surfaces. The word conductors are located on the first surface. Each word conductor is connected to a corresponding word line driving circuit. The bit line conductors are located on the second surface. Each bit line conductor is connected to a corresponding bit line driving circuit and a corresponding sense amplifier by one or more disconnect switches. A disconnect switch is set to an open state if the bit line conductor connected to that disconnect switch is shorted to one of the word conductors.

Abstract: In a method for operating a passive matrix-addessable ferroelectric or electret memory device comprising memory cells in the form of a ferroelectric or electret thin-film polarizable memory material exhibiting hysteresis, particularly a ferroelectric or electret polymer thin film, and a first set of parallel electrodes forming word line electrodes in the device and a second set of parallel electrodes forming bit lines in the device, the word lines being oriented orthogonally to the bit lines, such that the word lines and bit lines are in direct contact with the memory cells, which can be set to either of two polarization states or switched between these by applying a switching voltage larger than a coercive voltage of the memory material between a word line and a bit line, a voltage pulse protocol with at least one disturb generating operation cycle is applied for switching selected addressed cells to determined polarization state.

Abstract: A sensing device for reading data stored in a passive matrix memory including memory cells in the form of ferroelectric capacitors, includes an integrator circuit for sensing the current response and a device for storing and comparing two consecutive read values, one of which is a reference value. In a read method for use with the sensing device a bit line is connected to the sensing device for sensing a charge flowing therebetween and a memory cell at the crossing of the former and activated word line, whereafter two consecutive reads of the memory cell are performed and integrated over predetermined time periods in order to generate first and second read values which are compared for determining a logical value dependent on the sensed charge.

Abstract: In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, first and second sets (14; 15) of addressing electrodes constitute word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) with each segments sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit line (BL) of a segment (S) with a sensing means (26), thus enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL) of the segment (S). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logical value.

Abstract: A sensing device (10) for reading data stored in a passive matrix memory comprising memory cells in the form of ferroelectric capacitors, comprises an integrator circuit (11) for sensing the current response and means (16,17,18) for storing and comparing two consecutive read values, one of which is a reference value.

Abstract: In a non-volatile passive matrix memory device comprising an electrically polarizable dielectric memory material exhibiting hysteresis between first and second sets of addressing electrodes, the electrodes of the first set are word lines and the electrodes of the second set are bit lines of the memory device. A memory cell with a capacitor-like structure is defined in the memory material at the overlap between a word line and a bit line. The word lines are divided into segments with each segments sharing and being defined by adjoining bit lines and means are provided for connecting each bit line of a segment with a sensing means, thus enabling simultaneous connections of all memory cells of a word line segment for readout via the bit lines of the segment. Each sensing means senses the charge flow in a bit line in order to determine a logical value stored in a memory cell defined by the bit line.

Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of a FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

Abstract: A magnetic memory cell for storing binary encoded data and a memory constructed from these memory cells. The memory cell stores information in the direction of magnetization of a torroidal layer of magnetic material. The memory cell is constructed from a structure having a top electrode, a soft layer which includes a planar sheet of a soft magnetic material, a hard layer which includes a planar sheet of a hard magnetic material, and a bottom electrode, the soft and hard layers being sandwiched between the top and bottom electrodes. The various layers are torroids. The hard and soft materials are chosen such that the magnitude to the magnetic field needed to magnetize the hard magnetic material is greater than the magnitude of the magnetic field needed to magnetize the soft magnetic material. The memory cell also includes a write circuit that generates first and second magnetic fields.

Abstract: A sense amplifier for comparing the resistance of a reference cell connected to a reference bit line to the resistance of a data cell connected to a data bit line. The amplifier includes a first terminal for connecting the sense amplifier to the reference bit line and a second terminal for connecting the sense amplifier to the data bit line. A reference current to voltage amplifier is connected to the first terminal for generating a reference voltage related to the current flowing through the reference bit line and for maintaining the first terminal at a reference potential when the current flowing through the reference bit line is less than a first current value. A data current to voltage amplifier is connected to the second terminal for generating a data voltage related to the current flowing through the data bit line and for maintaining the second terminal at the reference potential when the current flowing through the data bit line is less than a second current value.

Abstract: A magnetic memory cell for storing binary encoded data and a memory constructed from these memory cells. A memory cell according to the present invention stores information in the direction of magnetization of a layer of magnetic material. The memory cell is constructed from a structure having a top electrode, a soft layer which includes a planar sheet of a soft magnetic material, a hard layer which includes a planar sheet of a hard magnetic material, and a bottom electrode, the soft and hard layers being sandwiched between the top and bottom electrodes. The hard and soft materials are chosen such that the magnitude to the magnetic field needed to magnetize the hard magnetic material is greater than the magnitude of the magnetic field needed to magnetize the soft magnetic material. The memory cell also includes a write circuit that generates first and second magnetic fields. The first and second magnetic fields are parallel to the planar sheet of the soft layer.

Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

Abstract: A high density non-volatile ferroelectric-based memory based on a ferroelectric FET operated in a two terminal write mode. Storage words may be constructed either from one or two bit storage cells based on a ferroelectric FET. A memory using either the one or two bit storage cells includes a plurality of word storage cells organized into a rectangular array including a plurality of columns and rows. Each of the word storage cells includes N single bit memory cells. Each of the single bit memory cells includes a pass transistor and a ferroelectric storage element. All of the gate electrodes in the circuit are connected to a common gate electrode, and all of the source electrodes are connected to a common source electrode. If the memory is built from two bit storage cells as described herein, each storage cell is one half of a two bit storage cell.

Abstract: A memory based on a ferroelectric FET, the ferroelectric FET includes a gate electrode, a layer of ferroelectric material, layer of semiconducting material, a source electrode and a drain electrode. The layer of ferroelectric material is sandwiched between the gate electrode and the layer of semiconducting material, the source and drain electrodes being in contact with the layer of semiconducting material and spaced apart from one another. The memory includes a circuit for setting the ferroelectric FET to one of two states. The first state is set by applying a first voltage to the source and drain electrodes and a second voltage to the gate electrode. The second state is set by applying a third voltage to the gate and drain electrodes and fourth voltage to the source electrode. This arrangement reduces the number of pass transistors needed per ferroelectric FET to one plus a simple pulsing circuit that must be included with each word of memory.