Abstract: Reduction of the complexity of a Viterbi-type sequence detector is disclosed. It was based on elimination of less probably taken branches in the trellis. The method is applied to the design of the E2PR4 channel with 8/9 rate sliding block trellis code. Coding, by itself eliminates two states by coding constraints, and the disclosed method reduces the number of required ACS units from 14 to 11, while reducing their complexity as well. For the implementation of E2PR4 detection, 4 4-way, 3 3-way, 3 2-way and one 1-way ACSs are needed. System simulations show no BER performance drop at common SNRs when compared with a full 16-state E2PR4 implementation in magnetic disk drives.

Abstract: A method and apparatus for implementing a noise generator in an integrated circuit read channel to optimize the performance of the signal channel. In the preferred embodiment resistors are used to generate noise. The noise source is buffered and the noise signal passes through a pre-amplifier stage. A differential current digital-to-analog converter controlled multiplier cell controls the amplitude of the noise signal. A switch connects the noise signal to a differential current output buffer, which is coupled to a signal channel.

Abstract: In accordance with the invention, a system which compensates nonlinear bit shift is provided for a high-rate constant density recording device. The invention's apparatus generates a programmable write precompensation delay that is an accurate percentage of the write current time period, allowing for variations of the write current time period with the track radius. The apparatus utilizes the output tinning signal from a Voltage Controlled Oscillator VCO to generate write precompensation delay that is an accurate percentage of the VCO output timing signal period, equal to the write current time period. Differential ramp voltage signal, also generated in the VCO, is compared to the late threshold voltage regulated by two internal resistors. Trailing edge of the delayed write signal, created at the comparator's output, is varied with the change in late threshold voltage. Frequency of the VCO's output timing signal is varied for different tracks.

Abstract: A method and apparatus for timing acquisition of partial response class IV Signaling is described. The invention uses an acquisition logic block to determine an output sequence that best matches a preamble pattern. The logic block analyzes current quantizer output X and the two previous decisions X.sub.n and X.sub.n-1. The logic uses these values to determine the next value X.sub.n+1 so that the best match occurs. The invention is implemented with OR gates, AND gates, and D flip-flops and can operate in acquiring mode or tracking mode.