Patents by Inventor Richard YEN
Richard YEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240108844Abstract: A humidification system can include a heater base, a humidification chamber, and a breathing circuit. A cartridge can be removably coupled to the heater base. The cartridge can include various sensors, probes, sensor wire connectors, heater wire connectors, and/or other features. The cartridge can include features configured to mate with corresponding features on the humidification chamber and the heater base. The cartridge includes a memory, such as an EEPROM, or other suitable storage device. When the cartridge is installed on the heater base, the memory is electrically connected to a processor and/or memory of the heater base. Various models of cartridges can be produced for use with different humidification chambers, breathing circuits, and/or therapies. A connector can be configured to couple an inspiratory conduit to an outlet port of the humidification chamber. The connector can provide a pneumatic connection to the outlet port and an electrical connection to the cartridge.Type: ApplicationFiled: September 20, 2023Publication date: April 4, 2024Inventors: Hamish Adrian OSBORNE, Gavin Walsh Millar, Stephen David Evans, Bruce Gordon Holyoake, James William Stanton, David Leon McCauley, Gareth Thomas McDermott, Nicholas James Michael McKenna, Myfanwy Jane Antica Norton, Adrian John Elsworth, Michael John Andresen, Jonathan Andrew George Lambert, Sandeep Singh Gurm, Tessa Hazel Paris, Joseph Nathaniel Griffiths, Ping Si, Christopher Gareth Sims, Elmo Benson Stoks, Dexter Chi Lun Cheung, Peter Alan Seekup, Po-Yen Liu, Richard Edward Lang, Paul James Tonkin, Ian Lee Wai Kwan
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Publication number: 20240095743Abstract: Methods and systems are presented for providing a framework that enables a computer system to analyze and compare changes to different account characteristics of different accounts that occurred over a time period. A code is generated for an account to represent changes to different account characteristics of the account within the time period. Changes to different account characteristics may be highlighted in the code using different colors or patterns. By analyzing the code, overlapping changes from different account characteristics that occurred within the same time frame may be detected. The different change patterns associated with the user account may then be used to assess a risk for the user account and/or a transaction involving the user account.Type: ApplicationFiled: November 4, 2022Publication date: March 21, 2024Inventors: Suryadeep Tiwari, Vidhya Chandrasekaran, Angadhjot Hundal, Richard Yen-Ching Lee
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Patent number: 10829364Abstract: A method includes the following operations: forming a piezoelectric substrate including a piezoelectric structure and a conductive contact structure, in which the piezoelectric structure has a conductive layer and a piezoelectric layer in contact with the conductive layer, and the conductive contact structure is electrically connected to the piezoelectric structure and protrudes beyond a principal surface of the piezoelectric substrate; forming a semiconductor substrate having a conductive receiving feature and a semiconductor device electrically connected thereto; aligning the conductive contact structure of the piezoelectric substrate with the conductive receiving feature of the semiconductor substrate; and bonding the piezoelectric substrate with the semiconductor substrate such that the conductive contact structure is in contact with the conductive receiving feature.Type: GrantFiled: January 3, 2018Date of Patent: November 10, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Ren Cheng, Richard Yen, Yi-Hsien Chang, Wei-Cheng Shen
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Publication number: 20180141800Abstract: A method includes the following operations: forming a piezoelectric substrate including a piezoelectric structure and a conductive contact structure, in which the piezoelectric structure has a conductive layer and a piezoelectric layer in contact with the conductive layer, and the conductive contact structure is electrically connected to the piezoelectric structure and protrudes beyond a principal surface of the piezoelectric substrate; forming a semiconductor substrate having a conductive receiving feature and a semiconductor device electrically connected thereto; aligning the conductive contact structure of the piezoelectric substrate with the conductive receiving feature of the semiconductor substrate; and bonding the piezoelectric substrate with the semiconductor substrate such that the conductive contact structure is in contact with the conductive receiving feature.Type: ApplicationFiled: January 3, 2018Publication date: May 24, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Ren CHENG, Richard YEN, Yi-Hsien CHANG, Wei-Cheng SHEN
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Patent number: 9862592Abstract: A MEMS transducer includes a first substrate and a second substrate facing the first substrate. The first substrate includes a piezoelectric diaphragm and a conductive contact structure. The conductive contact structure is electrically connected to the piezoelectric diaphragm, and protrudes beyond a principal surface of the first substrate. The second substrate includes a conductive receiving feature and an active device. The conductive receiving feature is aligned with and further bonded to the conductive contact structure. The active device is electrically connected to the piezoelectric diaphragm through the conductive receiving feature and the conductive contact structure.Type: GrantFiled: March 13, 2015Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Ren Cheng, Richard Yen, Yi-Hsien Chang, Wei-Cheng Shen
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Publication number: 20160264399Abstract: A MEMS transducer includes a first substrate and a second substrate facing the first substrate. The first substrate includes a piezoelectric diaphragm and a conductive contact structure. The conductive contact structure is electrically connected to the piezoelectric diaphragm, and protrudes beyond a principal surface of the first substrate. The second substrate includes a conductive receiving feature and an active device. The conductive receiving feature is aligned with and further bonded to the conductive contact structure. The active device is electrically connected to the piezoelectric diaphragm through the conductive receiving feature and the conductive contact structure.Type: ApplicationFiled: March 13, 2015Publication date: September 15, 2016Inventors: Chun-Ren CHENG, Richard YEN, Yi-Hsien CHANG, Wei-Cheng SHEN
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Patent number: 9054854Abstract: Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of this “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.Type: GrantFiled: June 10, 2014Date of Patent: June 9, 2015Assignee: Altera CorporationInventor: Richard Yen-Hsiang Chang
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Patent number: 8774305Abstract: Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of this “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.Type: GrantFiled: June 3, 2013Date of Patent: July 8, 2014Assignee: Altera CorporationInventor: Richard Yen-Hsiang Chang
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Patent number: 8477897Abstract: Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of this “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.Type: GrantFiled: September 12, 2008Date of Patent: July 2, 2013Assignee: Altera CorporationInventor: Richard Yen-Hsiang Chang
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Patent number: 7800405Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: June 15, 2009Date of Patent: September 21, 2010Assignee: Altera CorporationInventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
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Patent number: 7623609Abstract: Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates.Type: GrantFiled: October 10, 2008Date of Patent: November 24, 2009Assignee: Altera CorporationInventors: Richard Yen-Hsiang Chang, Gregory Starr
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Publication number: 20090267645Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: ApplicationFiled: June 15, 2009Publication date: October 29, 2009Applicant: Altera CorporationInventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
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Patent number: 7557608Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: August 1, 2006Date of Patent: July 7, 2009Assignee: Altera CorporationInventors: Andy L Lee, Wanli Chang, Cameron McClintock, John E Turner, Brian D Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G Cliff
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Publication number: 20090041170Abstract: Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates.Type: ApplicationFiled: October 10, 2008Publication date: February 12, 2009Inventors: Richard Yen-Hsiang Chang, Gregory Starr
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Patent number: 7453968Abstract: Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates.Type: GrantFiled: May 18, 2004Date of Patent: November 18, 2008Assignee: Altera CorporationInventors: Richard Yen-Hsiang Chang, Gregory Starr
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Patent number: 7440532Abstract: Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of the “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.Type: GrantFiled: April 21, 2004Date of Patent: October 21, 2008Assignee: Altera CorporationInventor: Richard Yen-Hsiang Chang
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Patent number: 7242229Abstract: A PLL circuit is described. The PLL circuit includes: a signal generator and at least one divider coupled to the signal generator, where the at least one divider is programmable in user mode. In one embodiment, the PLL circuit includes a memory device associated with the at least one divider, where the memory device receives settings data and provides settings data to the at least one divider in user mode.Type: GrantFiled: May 3, 2002Date of Patent: July 10, 2007Assignee: Altera CorporationInventors: Gregory W. Starr, Richard Yen-Hsiang Chang, Edward P. Aung
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Patent number: 7096345Abstract: A data processing system for executing a plurality of instructions having a prescribed program order comprises a register file, a reorder buffer, and a plurality of functional units. The register file includes a plurality of registers to store data. The reorder buffer includes N buffer locations of which M buffer locations are bypassable and N?M buffer locations are non-bypassable, wherein N and M are integers and N>M. Each functional unit is capable of executing instructions regardless of the prescribed program order. The reorder buffer temporarily stores data corresponding to the plurality of instructions. When data of one of the plurality of instructions to be executed by a corresponding one of the plurality of functions units is temporarily stored in one of the M bypassable buffer locations, the reorder buffer transfers the data in one of the bypassable M buffer locations to the corresponding one of the functional units in order to execute the instruction.Type: GrantFiled: September 26, 2003Date of Patent: August 22, 2006Assignee: Marvell International Ltd.Inventors: Hong-Yi Hubert Chen, Richard Yen-Ching Lee, Geoffrey Yung, Jensen Tjeng
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Patent number: 6842040Abstract: At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.Type: GrantFiled: December 13, 2002Date of Patent: January 11, 2005Assignee: Altera CorporationInventors: Wanli Chang, Andy Lee, Cameron McClintock, Richard Cliff, Richard Yen-Hsiang Chang
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Patent number: 6661253Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: August 16, 2001Date of Patent: December 9, 2003Assignee: Altera CorporationInventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff