Patents by Inventor Richard Zeman

Richard Zeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7550996
    Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: June 23, 2009
    Assignee: Easic Corporation
    Inventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Levinthal, Richard Zeman
  • Patent number: 7157937
    Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: January 2, 2007
    Assignee: eASIC Corporation
    Inventors: Adrian Apostol, Petrica Avram, Romeo Iacobut, Adam Levinthal, Zvi Or-Bach, Ze′ev Wurman, Richard Zeman, Alon Kapel, George C. Grigore
  • Patent number: 7098691
    Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: August 29, 2006
    Assignee: eASIC Corporation
    Inventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Leventhal, Richard Zeman
  • Publication number: 20060164121
    Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.
    Type: Application
    Filed: March 3, 2006
    Publication date: July 27, 2006
    Applicant: Easic Corporation
    Inventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Levinthal, Richard Zeman
  • Publication number: 20060028241
    Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
    Type: Application
    Filed: July 22, 2005
    Publication date: February 9, 2006
    Applicant: eASIC Corporation
    Inventors: Adrian Apostol, Petrica Avram, Romeo Iacobut, Adam Levinthal, Zvi Or-Bach, Ze'ev Wurman, Richard Zeman, Alon Kapel, George Grigore
  • Publication number: 20060022705
    Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
    Type: Application
    Filed: July 27, 2004
    Publication date: February 2, 2006
    Applicant: eASIC Corporation
    Inventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Leventhal, Richard Zeman
  • Patent number: 6642744
    Abstract: This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: November 4, 2003
    Assignee: eASIC Corporation
    Inventors: Zvi Or-Bach, Ze'ev Wurman, Richard Zeman, Laurance Cooke
  • Publication number: 20020043988
    Abstract: This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.
    Type: Application
    Filed: October 5, 2001
    Publication date: April 18, 2002
    Inventors: Zvi Or-Bach, Ze?apos;ev Wurman, Richard Zeman, Laurance Cooke
  • Patent number: 6331790
    Abstract: This invention discloses a customizable and programmable integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for customization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: December 18, 2001
    Assignee: eASIC Corporation
    Inventors: Zvi Or-Bach, Ze'ev Wurman, Richard Zeman, Laurance Cooke