Abstract: Various implant holding systems are provided herein that include an outer tube, an inner tube, and a holder. The implant holding systems can be designed to hold various implants, such as bone anchors used in spinal operations. For example, one embodiment of an implant holding system can have an outer tube, an inner tube that can be disposed within the outer tube, and an implant holder that can be disposed within the inner tube. An individual bone anchor that has various configurations and sizes can be disposed within the holder, and the holder can engage the bone anchor to assist in maintaining an orientation of the bone anchor relative to the holder.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Abstract: According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Abstract: According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.

Abstract: According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

Abstract: A page virtualization table (PVT) and one or more block virtualization tables (BVTs) are maintained. The PVT includes PVT entries, each mapping a logical page number (LPN) to a virtual page number (VPN). Each BVT includes BVT entries, each mapping a virtual block number (VBN) to a physical block number (PBN). A request is received for accessing data stored in one of flash memory devices, the request including a first LPN. A search is performed in the PVT based on the first LPN to locate a first PVT entry to obtain a first VPN from the first PVT entry. A search is performed in a first BVT to locate a first BVT entry based on the VPN to obtain a first PBN from the first BVT entry. An input and output (IO) request is issued based on the first PBN to a flash controller associated with a first flash memory device that stores data corresponding to the first PBN.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: An alignment spacer having a diameter for use in a magnetic encoder apparatus for controlling the alignment of a magnet to a sensor ship having a major surface defining a reference plane includes a surface having at least one tab extending outwardly from the periphery of the surface. A raised portion extends from the surface defining an opening for receiving the sensor chip.

Abstract: A system and method for providing a safety alert for a device is disclosed. The invention minimizes or prevents the affects of programming errors and/or provides enhanced alert information to a monitoring healthcare provider, wherein the alert information may relate to a potential safety concern. The method includes monitoring data transmitted from a device and comparing the data to pre-established rules. When the data violates the rules, the system compiles an alert information packet, wherein the alert information packet includes information related to the device and the data. The system then transmits the alert information packet and/or an enhanced alert to multiple computer screens in a particular area.

Abstract: A magnetic encoder apparatus comprising a housing is disclosed in the present invention. The housing includes a base portion and a cover plate portion. The housing also comprises a magnet that is contained in the base portion of the housing, a sensor chip having a major surface located adjacent to the magnet, and an alignment spacer comprising a first side and a second side. The first side of the alignment spacer having an opening through to the second side of the alignment spacer, and the second side fitting into the base portion of the housing. The opening of the alignment spacer encloses the sensor chip.

Abstract: A magnetic encoder apparatus has a housing that includes a base portion and a cover plate portion. The housing also has a magnet that is contained in the base portion of the housing, a sensor chip having a major surface located adjacent to the magnet, and an alignment spacer having a first side and a second side. The first side of the alignment spacer has an opening through to the second side of the alignment spacer, and the second side fits into the base portion of the housing. The opening of the alignment spacer encloses the sensor chip.

Abstract: A system and method for providing a safety alert for a device is disclosed. The invention minimizes or prevents the affects of programming errors and/or provides enhanced alert information to a monitoring healthcare provider, wherein the alert information may relate to a potential safety concern. The method includes monitoring data transmitted from a device (e.g., infusion pump) and comparing the data to pre-established rules. When the data violates the rules, the system compiles an alert information packet, wherein the alert information packet includes information related to the device and the data. The system then transmits the alert information packet and/or an enhanced alert to multiple computer screens in a particular area.

Abstract: A valve sealing flange for sealing fluid ports in a valve is provided, comprising a flexible planar portion having first and second opposed surfaces, spaced-apart, elongated, tapered protrusions extending upwardly from the first surface of said sealing flange, the protrusions being configured and positioned on the surface of the planar portion to mate with fluid ports located within a side surface of a valve when the valve sealing flange is placed thereon to effect sealing of the ports, and spaced-apart protrusions extending from the second surface of thesealing flange, the protrusions being of such configuration and spacing to support the sealing flange in a substantially level position when attached to the valve.

Abstract: A magnetic encoder apparatus comprising a housing is disclosed in the present invention. The housing includes a base portion and a cover plate portion. The housing also comprises a magnet that is contained in the base portion of the housing, a sensor chip having a major surface located adjacent to the magnet, and an alignment spacer comprising a first side and a second side. The first side of the alignment spacer having an opening through to the second side of the alignment spacer, and the second side fitting into the base portion of the housing. The opening of the alignment spacer encloses the sensor chip.