Abstract: A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device having a substrate at the backside, dielectric layers on the substrate, metal layers interleaved with the dielectric layers, and a through silicon via (TSV) formed in the backside through the substrate and the dielectric layers. TSV seal rings may be formed around the TSV to protect the semiconductor device from moisture and/or water ingress. The TSV seal rings may be coupled to a high-voltage cathode bond pad and be coupled to offset portions of one of the metal layers to reduce leakage and/or parasitic effects due to the voltage difference between the cathode and the substrate. The TSV seal rings may also be merged with die seal rings at the edge of the substrate.

Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.

Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.

Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.

Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide layer of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.

Abstract: Systems and methods for facilitating lift-off processes are provided. In one embodiment, a method for pattering a thin film on a substrate comprises: depositing a first sacrificial layer of photoresist material onto a substrate such that one or more regions of the substrate are exposed through the first sacrificial layer; depositing a protective layer over at least part of the first sacrificial layer; partially removing the first sacrificial layer to form at least one gap between the protective layer and the substrate; depositing an optical coating over the protective layer and the one or more regions of the substrate exposed through the first sacrificial layer, wherein the optical coating deposited over the protective layer is separated by the at least one gap from the optical coating deposited over the regions of the substrate exposed through the first sacrificial layer; and removing the first sacrificial layer.

Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.

Abstract: An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region.