Patents by Inventor Rick Carlton Jerome

Rick Carlton Jerome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9257525
    Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: February 9, 2016
    Assignee: Intersil Americas LLC
    Inventors: I-Shan Sun, Rick Carlton Jerome, Francois Hebert
  • Patent number: 8691670
    Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide layer of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 8, 2014
    Assignee: Soitec
    Inventors: Rick Carlton Jerome, Francois Hebert, Craig McLachlan, Kevin Hoopingarner
  • Publication number: 20120293474
    Abstract: Systems and methods for facilitating lift-off processes are provided. In one embodiment, a method for pattering a thin film on a substrate comprises: depositing a first sacrificial layer of photoresist material onto a substrate such that one or more regions of the substrate are exposed through the first sacrificial layer; depositing a protective layer over at least part of the first sacrificial layer; partially removing the first sacrificial layer to form at least one gap between the protective layer and the substrate; depositing an optical coating over the protective layer and the one or more regions of the substrate exposed through the first sacrificial layer, wherein the optical coating deposited over the protective layer is separated by the at least one gap from the optical coating deposited over the regions of the substrate exposed through the first sacrificial layer; and removing the first sacrificial layer.
    Type: Application
    Filed: September 15, 2011
    Publication date: November 22, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: I-Shan Sun, Francois Hebert, Rick Carlton Jerome
  • Publication number: 20120288083
    Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.
    Type: Application
    Filed: October 27, 2011
    Publication date: November 15, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: I-Shan Sun, Rick Carlton Jerome, Francois Hebert
  • Publication number: 20110140232
    Abstract: An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 16, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Stephen J. Gaul, Michael D. Church, Rick Carlton Jerome