Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: Techniques to manage various errors in memory such as, e.g., NAND memory in electronic devices are disclosed. In some embodiments, erase, read, and program error handling errors are managed.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: The above-described methods and computer system describe the use of dynamic addressing, lazy relocations and erases, and page state information to provide fast disk caching and solid state disk applications using solid-state nonvolatile memories. The approach reduces write-latencies for demand requests, as well as the number of erase cycles on erase blocks.

Abstract: One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is written back to the memory location from where it was read in order to preserve it. If the data is found to be invalid (corrupted) then a failure codeword is written in the memory location to indicate a failure of the memory location. The failure codeword may be preselected or dynamically calculated so that it has a mathematical distance greater than all correctable data patterns.

Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

Abstract: An integrated circuit includes a trace analyzer to sample, process and store data carried along internal or external data path of the circuit. The trace analyzer may include a multiplexer, a sampler, a formatter and a memory controller. The trace analyzer samples data on a predetermined basis, processes it and caused the processed data to be stored in a memory.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.

Abstract: An apparatus is equipped with a disk block allocation optimization function for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of file accesses. The function includes logic for tracing the sequence of logical file accesses, then mapping the traced logical file accesses to physical disk blocks to determine the current disk block allocation, logic for generating the alternative disk block allocation, if possible, using the physical trace results, and logic for effectuating the alternate disk block allocation, if generated. In one particular embodiment, the logic for generating the alternative disk block allocation employs a random search approach, while in another embodiment, the logic for generating the alternative disk block allocation employs a heuristic approach.

Abstract: One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is written back to the memory location from where it was read in order to preserve it. If the data is found to be invalid (corrupted) then a failure codeword is written in the memory location to indicate a failure of the memory location. The failure codeword may be preselected or dynamically calculated so that it has a mathematical distance greater than all correctable data patterns.

Abstract: A computer system is equipped with an operating system having a tracer driver for generating trace data including disk locations accessed for disk accesses made by various components of the operating system during system startup/boot time. The tracer driver is loaded at an initial phase of system start-up. The computer system is further equipped with a companion disk block relocation driver for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of disk accesses. In some embodiments, the disk block relocation driver includes logic for tracing the sequence of disk accesses to determine the current disk block allocation, logic for generating the alternative disk block allocation, if possible, using the trace results, and logic for effectuating the alternate disk block allocation, if generated.

Abstract: A computer system is programmed with a plurality of programming instructions for implementing a software function, having an installation utility with logic for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of disk accesses. In some embodiments, the logic includes logic for tracing the sequence of disk accesses to determine the current disk block allocation, logic for generating the alternative disk block allocation, if possible, using the trace results, and logic for effectuating the alternate disk block allocation, if generated. In one particular embodiment, the logic for generating the alternative disk block allocation employs a random search approach, while in another embodiment, the logic for generating the alternative disk block allocation employs a heuristic approach.