Abstract: A folding camper has a body having a lower end configured for positioning within a bed of a pickup truck or on a trailer. The camper has sidewalls rotationally engaged between the roof and body whereby the folding camper is moveable between a collapsed position wherein a first sidewall and a second sidewall and a front wall and rear wall are all folded to a substantially horizontal positioning, to a deployed positioning wherein the roof is elevated above an upper end of the body with the first sidewall and the second sidewall both rotated to a substantially vertical positioning.

Abstract: A folding camper has a body having a lower end configured for positioning within a bed of a pickup truck or on a trailer. The camper has sidewalls rotationally engaged between the roof and body whereby the folding camper is moveable between a collapsed position wherein a first sidewall and a second sidewall and a front wall and rear wall are all folded to a substantially horizontal positioning, to a deployed positioning wherein the roof is elevated above an upper end of the body with the first sidewall and the second sidewall both rotated to a substantially vertical positioning.

Abstract: A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.

Abstract: A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface.

Abstract: A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface.

Abstract: A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).

Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.