Patents by Inventor Rickie C. Lake
Rickie C. Lake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9737947Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.Type: GrantFiled: January 27, 2014Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Rickie C. Lake, William M. Hiatt
-
Patent number: 9612409Abstract: A hermetically sealable package may be formed from a top portion and a bottom portion mated along a seam at or near a plane of an optical fiber. A completed pill assembly may be positioned directly into the enclosure base without requiring the fiber to be threaded through the feed through or “snout”. The top potion may then be mated with the bottom portion to form the package. A glass solder ring may be placed coaxial with the fiber in the feed through. The seam may be sealed by laser welding and the glass solder ring reflowed by laser heating, for example, with a same laser as used to weld the seam or by resistive or induction heating.Type: GrantFiled: September 15, 2003Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Marc A. Finot, Rickie C. Lake
-
Patent number: 9153491Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.Type: GrantFiled: September 11, 2014Date of Patent: October 6, 2015Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
-
Publication number: 20150031171Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.Type: ApplicationFiled: September 11, 2014Publication date: January 29, 2015Inventor: Rickie C. Lake
-
Publication number: 20140284375Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.Type: ApplicationFiled: January 27, 2014Publication date: September 25, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Warren M. Farnworth, Rickie C. Lake, William M. Hiatt
-
Patent number: 8835293Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.Type: GrantFiled: March 26, 2012Date of Patent: September 16, 2014Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
-
Patent number: 8415233Abstract: Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool.Type: GrantFiled: June 13, 2011Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
-
Publication number: 20120186741Abstract: An apparatus for bonding semiconductor wafers together including a moveable upper bond head and a resilient member positioned on a surface of the bond head for contacting a first wafer that is positioned at an elevation below the upper bond head. The resilient member is configured to apply a force onto a top side surface of the first wafer thereby compressing the first wafer against a second wafer that is positioned at an elevation below the first wafer. A method of wafer to wafer bonding includes the steps of positioning at least two wafers beneath the moveable upper bond head, positioning the resilient member in physical contact with one of the at least two wafers, and resiliently deforming the resilient member as it is moved into contact with the wafer to facilitate bonding of the wafers.Type: ApplicationFiled: March 2, 2011Publication date: July 26, 2012Applicant: APTINA IMAGING CORPORATIONInventor: RICKIE C. LAKE
-
Publication number: 20120175341Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.Type: ApplicationFiled: March 26, 2012Publication date: July 12, 2012Applicant: MICRON TECHNOLOGY, INC.Inventor: Rickie C. Lake
-
Patent number: 8183151Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.Type: GrantFiled: May 4, 2007Date of Patent: May 22, 2012Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
-
Publication number: 20110233705Abstract: Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool.Type: ApplicationFiled: June 13, 2011Publication date: September 29, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Rickie C. Lake
-
Patent number: 7972940Abstract: Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool.Type: GrantFiled: December 28, 2007Date of Patent: July 5, 2011Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
-
Patent number: 7968042Abstract: A method and apparatus for molding a structure on the top surface of a substrate. Mold material is dispensed onto an area of the top surface of the substrate. The mold apparatus is positioned over the area. The mold portion of the mold apparatus is positioned above the mold material and the mold material is surrounded with a shroud of the mold apparatus. A seal is formed between the shroud and the top surface of the substrate. The pressure is reduced within the shroud to below the ambient pressure. The mold portion of the mold apparatus is lowered toward the top surface of the substrate, so that at least the outer edge of the mold portion is in contact with the mold material. The pressure within the shroud is raised to at least the ambient pressure, and the mold material is cured to form the structure.Type: GrantFiled: April 16, 2008Date of Patent: June 28, 2011Assignee: Aptina Imaging CorporationInventor: Rickie C. Lake
-
Patent number: 7927916Abstract: An optic wafer for assembly with an imager wafer, the optic wafer comprising a plurality of reliefs in a surface thereof coincident with street locations separating mutually adjacent optic element locations. A wafer assembly that includes the optic wafer and an imager wafer and methods of dicing a wafer assembly are also disclosed.Type: GrantFiled: April 4, 2007Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
-
Patent number: 7888758Abstract: A carrier wafer for wafer level fabrication of imager structures comprising a substrate with trenches corresponding to locations of imager arrays on an imager wafer. A method of fabricating such a carrier wafer and a method of fabricating an imager module employing such a carrier wafer are also provided.Type: GrantFiled: March 12, 2008Date of Patent: February 15, 2011Assignee: Aptina Imaging CorporationInventor: Rickie C. Lake
-
Patent number: RE42773Abstract: The present invention teaches a method of manufacturing an enclosed transceiver, such as a radio frequency identification (“RFID”) tag. Structurally, in one embodiment, the tag comprises an integrated circuit (IC) chip, and an RF antenna mounted on a thin film substrate powered by a thin film battery. A variety of antenna geometries are compatible with the above tag construction. These include monopole antennas, dipole antennas, dual dipole antennas, a combination of dipole and loop antennas. Further, in another embodiment, the antennas are positioned either within the plane of the thin film battery or superjacent to the thin film battery.Type: GrantFiled: December 4, 2003Date of Patent: October 4, 2011Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, John R. Tuttle, Rickie C. Lake
-
Patent number: RE42872Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. Flexible radio frequency identification (RFID) devices are coupled to a roll of flexible material. Each RFID device coupled to the roll is advanced into a wireless communication region. An antenna in the region separately communicates with each of the RFID devices in a manner that isolates the communication from other REID devices counted to the roll outside the region.Type: GrantFiled: November 24, 2004Date of Patent: October 25, 2011Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
-
Patent number: RE43918Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. An RFID tag and interrogator may each include a transmitter and a receiver. The tag and interrogator may communicate with each other at different frequency bands and may communicate in accordance with a wireless communication protocol.Type: GrantFiled: September 28, 2007Date of Patent: January 8, 2013Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
-
Patent number: RE43935Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. An RFID tag and interrogator may each include a transmitter and a receiver. The tag and interrogator may communicate with each other at different frequency bands and may communicate in accordance with a wireless communication protocol.Type: GrantFiled: September 28, 2007Date of Patent: January 15, 2013Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
-
Patent number: RE43940Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. An RFID tag and interrogator may each include a transmitter and a receiver. The tag and interrogator may communicate with each other at different frequency bands and may communicate in accordance with a wireless communication protocol.Type: GrantFiled: September 28, 2007Date of Patent: January 22, 2013Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle