Patents by Inventor Ricky Amos
Ricky Amos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7863083Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.Type: GrantFiled: August 25, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Ricky Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Alessandro C. Callegari, Supratik Guha, Hyungjun Kim, Fenton R. McFeely, Vijay Narayanan, Kenneth P. Rodbell, John J. Yurkas
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Publication number: 20080311745Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.Type: ApplicationFiled: August 25, 2008Publication date: December 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Douglas A. Buchanan, Cyril Cabral, JR., Alessandro C. Callegari, Supratik Guha, Hyungjun Kim, Fenton R. McFeely, Vijay Narayanan, Kenneth P. Rodbell, John J. Yurkas
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Publication number: 20060189061Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: April 19, 2006Publication date: August 24, 2006Inventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaren Surendra
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Publication number: 20060105515Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.Type: ApplicationFiled: November 10, 2005Publication date: May 18, 2006Inventors: Ricky Amos, Douglas Buchanan, Cyril Cabral, Evgeni Gousev, Victor Ku, An Steegen
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Publication number: 20050186747Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: February 25, 2004Publication date: August 25, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaran Surendra
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Publication number: 20050106788Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: ApplicationFiled: December 2, 2004Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Katayun Barmak, Diane Boyd, Cyril Cabral, Meikei Leong, Thomas Kanarsky, Jakub Kedzierski
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Publication number: 20050064690Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Douglas Buchanan, Cyril Cabral, Evgeni Gousev, Victor Ku, An Steegen
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Patent number: 6846734Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: GrantFiled: November 20, 2002Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Ricky Amos, Katayun Barmak, Diane C. Boyd, Cyril Cabral, Jr., Meikei Leong, Thomas S. Kanarsky, Jakub Tadeusz Kedzierski
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Publication number: 20040094804Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Katayun Barmak, Diane C. Boyd, Cyril Cabral, Meikei Leong, Thomas S. Kanarsky, Jakub Tadeusz Kedzierski
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Publication number: 20030098489Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2 (CO)10 as the source material is used when Re is to be deposited.Type: ApplicationFiled: November 29, 2001Publication date: May 29, 2003Applicant: International Business Machines CorporationInventors: Ricky Amos, Douglas A. Buchanan, Cyril Cabral, Alessandro C. Callegari, Supratik Guha, Hyungjun Kim, Fenton R. McFeely, Vijay Narayanan, Kenneth P. Rodbell, John J. Yurkas