Abstract: A method of controlling a switched capacitor voltage regulator includes modifying a topology factor associated with the switched capacitor voltage regulator in response to a change in output voltage associated with the switched capacitor voltage regulator, thereby maintaining an average output voltage associated with the switched capacitor voltage regulator. The method also includes modifying a loop delay associated with the switched capacitor voltage regulator in response to a change in operational frequency associated with the switched capacitor voltage regulator, thereby reducing ripple amplitude associated with the switched capacitor voltage regulator. A corresponding feedback/feed forward switched capacitor voltage regulator, controller, computer-readable medium, and voltage regulation system are also disclosed.

Abstract: A method of controlling a switched capacitor voltage regulator includes modifying a topology factor associated with the switched capacitor voltage regulator in response to a change in output voltage associated with the switched capacitor voltage regulator, thereby maintaining an average output voltage associated with the switched capacitor voltage regulator. The method also includes modifying a loop delay associated with the switched capacitor voltage regulator in response to a change in operational frequency associated with the switched capacitor voltage regulator, thereby reducing ripple amplitude associated with the switched capacitor voltage regulator. A corresponding feedback/feed forward switched capacitor voltage regulator, controller, computer-readable medium, and voltage regulation system are also disclosed.

Abstract: A startup circuit for use with a SCVR circuit includes a comparator operative to generate a first control signal as a function of a comparison between an output voltage generated by the SCVR circuit and a reference voltage, the first control signal being used to disable the startup circuit. The startup circuit further includes a reference generator and a controller. The reference generator is coupled with the comparator and operative to generate at least first, second and third voltages, the second voltage being greater than the first voltage, and the third voltage being greater than the second voltage. The controller is coupled with the reference generator and operative to dynamically select a given one of the first and third voltages as the reference voltage supplied to the comparator as a function of the first control signal.

Abstract: Described embodiments provide for a regulated voltage supply to a Universal Serial Bus (USB) system. The regulator comprises a pass device that might be coupled to a host device providing a bus voltage. An integrated USB physical layer (PHY) is coupled to the pass device through a control voltage signal pin. A regulation circuit is coupled to the integrated USB PHY, and the regulation circuit supplies about 3.3V from the bus voltage.

Abstract: Described embodiments provide for a regulated voltage supply to a Universal Serial Bus (USB) system. The regulator comprises a pass device that might be coupled to a host device providing a bus voltage. An integrated USB physical layer (PHY) is coupled to the pass device through a control voltage signal pin. A regulation circuit is coupled to the integrated USB PHY, and the regulation circuit supplies about 3.3V from the bus voltage.

Abstract: Disclosed is an external regulator reference voltage generator circuit that precisely controls the supply voltage applied to core logic to optimize the operational characteristics of the core logic 120 without using excessive power. An adaptive voltage and scaling optimization circuit 124 is used to detect the operating parameters of the core logic 120 and generate a voltage control signal to control a reference voltage regulator. The reference voltage regulator generates a regulator reference voltage in response to the voltage control signal that controls an external regulator which, in turn, generates the supply voltage.

Abstract: Disclosed is an external regulator reference voltage generator circuit that precisely controls the supply voltage applied to core logic to optimize the operational characteristics of the core logic 120 without using excessive power. An adaptive voltage and scaling optimization circuit 124 is used to detect the operating parameters of the core logic 120 and generate a voltage control signal to control a reference voltage regulator. The reference voltage regulator generates a regulator reference voltage in response to the voltage control signal that controls an external regulator which, in turn, generates the supply voltage.

Abstract: A comparator receives first differentials, compares the differentials to a positive offset, and sets bits dependent upon whether the differentials are greater than the positive offset. The comparator receives second differentials, compares the differentials to a negative offset, and sets bits dependent upon whether the differentials are greater than the negative offset. The comparator compares the first bits to the second bits, and sets a mask dependent upon whether the first bits and the second bits are identical. The comparator receives subsequent differentials, compares the differentials to a zero offset, and sets bits dependent upon whether the differentials are greater than the zero offset. The subsequent bits are compared to the mask and corrected.

Abstract: A comparator receives a first read of voltage differentials from a series of bit cells, compares the first read to a positive voltage offset of a given magnitude, and set bits in a first bit stream to values that are dependent upon whether the voltage differential from a given bit cell is greater than the positive voltage offset. The first bit stream is then stored in a first register. The comparator also receives a second read of the voltage differentials from the series of bit cells, compares the second read to a negative voltage offset of the given magnitude, and sets bits in a second bit stream to values that are dependent upon whether the voltage differential from a given bit cell is greater than the positive voltage offset. The second bit stream is stored in a second register. The comparator then compares the first bit stream to the second bit stream, and set bits in a mask string dependent upon whether the bits in a given position of the first bit stream and the second bit stream are identical.

Abstract: An XOR circuit includes XOR function logic. One advantage of the XOR circuit is that the complements of A and B are not required. The XOR circuit receives an enable signal that disables all the load transistors to eliminate static power dissipation of the XOR circuit and always force the output high when disabled. The output signal of the XOR function logic does not swing rail-to-rail and also has a relatively low drive level. To overcome that, cascade transistor stages are used that have small increments in device sizes, preferably widths, between stages. This allows the fastest rise/fall times at the output of the XOR function logic.

Abstract: An on-chip voltage reference supply operates in the current domain rather than the voltage domain, implemented with a single diode drop to reduce power supply headroom requirements. A plurality of current generators generate currents representing a first design voltage. A gain circuit responds to the currents to supply a gain voltage representing the sum of the first design voltages. A summing circuit sums the gain voltage and a second design voltage to derive the predetermined reference voltage.

Abstract: Data and strobe comparators are provided wherein each comparator includes a wide-swing bias circuit, an input stage, a current bias circuit, a load circuit, an output buffer and a clamp circuit. The wide-swing bias circuit, input stage, current bias circuit, load circuit, and a clamp circuit comprise a well-controlled preamplifier circuit. The input stage includes low-threshold transistors that receive differential inputs. The transistors form a single stage input. The low-threshold transistors turn on at several hundred millivolts, and from an operational perspective, almost immediately. The well-controlled aspect of preamplifier is achieved since all the transistors are made from the same semiconductor manufacturing process and have their physical dimensions precisely matched. An output buffer is connected to the preamplifier. Such a buffer is used for both data and strobe reception. The buffer includes a differential-to-single-ended converter that includes low-threshold transistors.

Abstract: The invention concerns differential amplifiers for computer disc drives, implemented in Metal Oxide Semiconductor (MOS) technology. The amplifiers are of the controllable-gain type. Gain is controlled by adjusting the channel current which passes through the differential Field-Effect Transistors (FETs) of the amplifier. The channel current can be viewed as having a constant component, to which is added an adjustment component. The adjustment component does not pass through the active loads of the differential amplifier, thereby allowing a larger change in gain to be attained.

Abstract: A CMOS motor drive for a disk drive spindle motor. The design of the drive circuit permits the integration of power electronics together with logic or other circuitry on a single integrated circuit wafer. For each motor phase the power electronics formed on the integrated circuit wafer includes a plurality of P-type and N-type MOSFET power transistor pairs and a plurality of corresponding output bonding pads; the drain terminals of each transistor pair being connected together to its corresponding output bonding pad. The wafer is enclosed in packaging which includes an output pin for providing an electrical connection to one phase of the disk drive spindle motor, and a plurality of bond wires corresponding to the plurality of output bonding pads, each bond wire providing an electrical connection between its corresponding bonding pad and the output pin. The transistor pairs and bond wires operate in parallel, each carrying an equivalent portion of the total current output presented at the output pin.

Abstract: An electrically controlled oscillator circuit having multi-phase outputs with programmable frequency. The circuit includes a ring oscillator having a plurality of inverting stages. Each stage has an output which is connected to a switch that can be programmed to select one of a plurality of capacitors with different values to change the frequency range of the oscillator. Controlled current is fed to the stages to vary the frequency of the oscillator within a selected frequency range. Using capacitors to change the frequency range of the oscillator reduces variations of the oscillator output frequency.

Abstract: An analog-to-digital inverter includes successive approximation control logic for generating ten-bit binary numbers, a digital-to-analog converter (DAC) having a resistor string and a weighted-capacitor array for converting the ten-bit binary output of the control logic to a known analog voltage, and an analog comparator for comparing the output of the DAC to a reference voltage provided via a tap to the mid-point of the DAC resistor string. The unknown analog voltage input to the ADC and the reference voltage are provided to the capacitor array to precharge the array to a voltage equal to the reference voltage minus the unknown analog voltage. The output of the DAC is therefore equal to the known analog voltage plus the reference voltage minus the unknown analog voltage.

Abstract: A bandgap voltage reference start-up circuit configured to initiate bandgap reference operation over an extended temperature range while being relatively insensitive to the effects of fabrication process variables. The circuit as preferably implemented includes a differential amplifier in the bandgap voltage reference stage which controls the source of current to contrasted bipolar devices situated in parallel paths. A comparator monitors the activities of the current source drive signal and compares that to an internally generated reference, which reference is configured to the matched in temperature and process variable effect the corresponding bandgap reference bipolar device and the current source device. During start-up the comparator initiates an injection of current into one bipolar device of the bandgap reference circuit to drive the bandgap loop into the appropriate of two potential operating states. The preferred embodiment also includes a power-down mode capability.

Abstract: In a motor speed or torque control circuit for an electronically commutated motor (ECM) used in a ceiling fan, a pulse width modulator operating at an above audible pulse repetition rate is used in combination with means to adjust the motor voltage to achieve a large (20 to 1) range of smooth fan speed adjustment. The pulse width modulator, which takes the form of a comparator, has as inputs an invariant sawtooth voltage waveform, and a smooth, adjustable control voltage dependent on the voltage supplied to the motor. A steady state or pulsed output is produced dependent on whether intersections occur at the comparator input. The active output state of the pulse width modulator is used to control the application of power to the motor. The control circuit permits speed or torque control from a wall location, or on the ceiling fixture combining the motor. The speed or torque control circuitry is designed for use in a maximally integrated ECM control circuit.

Abstract: The invention discloses a control circuit for an electronically commutated motor which performs essential internal commutation and control functions and responds to external controls, usually user operated. The invention is embodied in a ceiling fan which is subject to controls over motor speed or torque and direction of rotation. The control circuit uses a differential transconductance amplifier, which is periodically balanced, for commutation timing, and control logic, which includes a bidirectional counter, designed for uniformity in count duration, irrespective of the count, direction of counting, or changes in direction of counting, and a five rank decoding structure which selects the unenergized winding stage for sensing, selects the energized winding stages for suitably sensed energization, and responds to both direction and energy controls. The internal control includes circuit protection when power is first turned on.

Abstract: In a motor control circuit for an electronically commutated reversible motor used in a ceiling fan, a control is used to reduce the voltage supplied to the motor for variable speed or torque operation. At the same time, a substantially smooth control voltage, dependent on the variable voltage supplied to the motor, is produced. This control voltage, which is used to enhance the adjustment rate, is applied to control a pulse width modulator, which produces output pulses which also control the flow of energy to the motor. When the control voltage reaches a value slightly past the desired minimum speed or torque setting, a signal is generated to change the direction of motor rotation. Means are provided to delay the actual reversal to protect the power switches in the control circuit. When power is first applied, the initial direction of motor rotation is set by a switch on the ceiling fan. The control circuit permits control of motor reversal from a wall location.