Abstract: The state transition of a linear feedback shift register (LFSR) controlled by a clock (310) with length N and step size W, W being at least two, is accomplished via a next-state function (320). The next-state function deploys a state transition matrix (350). The state vector (330), which represents the contents of the LFSR, is either multiplied sequentially by the state transition matrix or multiplied by the state transition matrix to the power of W (multiple state transition matrix). The method and the LFSR according to the invention are characterized in that the multiple state transition matrix is decomposed in a first matrix (360) and a second matrix (370), the first matrix comprising at most N+W+1 different expressions and the second matrix comprising at most N+W+1 different expressions. The LFSR further comprises means to multiply the state vector by the second matrix and the first matrix, and means for computing the first matrix.

Abstract: Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vector processor would then be equipped with a plurality of generators which generate basic codes in vector format. However, a disadvantage of such a configurable vector processor is that it cannot provide a composite code which is dependent on such basic codes. This is necessary if the configurable vector processors should be flexible enough to support a variety of CDMA-like standards. The device according to the invention is provided with at least two weighted sum units, which are able to make a selection out of a plurality of incoming basic-code vectors by means of a weighted sum operation, under the control of a configuration word.