Patents by Inventor Ricky L. K. Chan

Ricky L. K. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6584436
    Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: June 24, 2003
    Assignee: Vast Systems Technology, Inc.
    Inventors: Graham R. Hellestrand, Ricky L. K. Chan, Ming Chi Kam, James R. Torossian
  • Publication number: 20020032559
    Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.
    Type: Application
    Filed: March 27, 2001
    Publication date: March 14, 2002
    Inventors: Graham R. Hellestrand, Ricky L.K. Chan, Ming Chi Kam, James R. Torossian
  • Publication number: 20020019969
    Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.
    Type: Application
    Filed: May 9, 2001
    Publication date: February 14, 2002
    Inventors: Graham R. Hellestrand, King Yin Cheung, James R. Torossian, Ricky L.k. Chan, Ming Chi Kam, Foo Ngok Yong
  • Patent number: 6263302
    Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: July 17, 2001
    Assignee: Vast Systems Technology Corporation
    Inventors: Graham R. Hellestrand, King Yin Cheung, James R. Torossian, Ricky L. K. Chan, Ming Chi Kam, Foo Ngok Yong
  • Patent number: 6230114
    Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: May 8, 2001
    Assignee: Vast Systems Technology Corporation
    Inventors: Graham R. Hellestrand, Ricky L. K. Chan, Ming Chi Kam, James R. Torossian