Abstract: Described is an apparatus for generating a thermometer code, the apparatus comprises: a 2-bit bi-directional shift register; and more than two multiplexers operable to form storage units and coupled together in a chain to generate the thermometer code, the more than two multiplexers controlled by outputs of the 2-bit bi-directional shift register.

Abstract: Described is an apparatus for generating a thermometer code, the apparatus comprises: a 2-bit bi-directional shift register; and more than two multiplexers operable to form storage units and coupled together in a chain to generate the thermometer code, the more than two multiplexers controlled by outputs of the 2-bit bi-directional shift register.

Abstract: A three-dimensional integrated capacitance structure comprises at least two arrays of “unit cells” on respective layers of an IC, with each unit cell comprising a center conductor and a conducting ring which surrounds the center conductor. Each array comprises a plurality of unit cells, tiled on a given IC layer at a predetermined pitch. The arrays are arranged vertically such that adjacent vertical arrays are offset in the x and y dimensions by a predetermined fraction—preferably ½—of the unit cells' pitch. The structure includes vias arranged to interconnect the arrays such that each center conductor is connected to a conducting ring of the array immediately above and/or below the center conductor, and such that each conducting ring is connected to a center conductor of the array immediately above and/or below the conducting ring.

Abstract: An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)×fref, for a natural number M and reference clock signal frequency fref.

Abstract: A register dump providing enhanced efficiency by using a transmission gate for generating a register word line signal so as to reduce clock loading, and by using a complementary gate for generating a precharged pull-down signal so as to reduce discharge time and register word line capacitive loading.