Abstract: A duplex controller with a pair of redundant processor circuits connected by an update bus for use in a system which requires high reliability. Each of the redundant processor circuits is individually capable of performing the tasks of the duplex controller, so that the controller remains operable when one of the processor circuit members fails. The update bus is connected so that when the active circuit member executes a write command, the write command is also effected at the standby circuit. In this manner the memory state of the standby is dynamically maintained so that when control of the duplex controller is transferred from the active to the standby to the standby circuit, the standby circuit is instantaneously ready with up to date information to assume all processing responsibilities of the duplex controller without unnecessary delay.