Abstract: A data processor includes an array of a plurality of processing elements haivng ports connected to neighboring elements. Elements at each end of a column have interconnected ports so that data can be sequentially cycled through the column elements. Elements at each end of a row have switchably interconnected ports so that in one mode data can be sequentially cycled through the row elements. The processor further includes a shift register switchably coupled to each row and memory apparatus coupled to the shift registers. The shift registers are switchable such that in a second mode data can be sequentially cycled through the shift registers and the corresponding row elements. The processor also includes an input shuffle matrix for reformatting data for facilitating data storage and recall during processing, thereby increasing overall system throughput.