Abstract: A cache controller includes a hit determination circuit that is adapted to handle a non-symmetric cache. This hit determination circuit includes symmetric match circuit having a first input port for receiving addresses from a host processor bus and a second input port for receiving a tag entry from a cache tag memory. The symmetric match circuit compares the address to the tag entry and generates a symmetric match signal when there is a match between the address and the tag entry. A non-symmetric circuit that includes a first input port for receiving an address from the host processor bus and a second input port for receiving a predetermined pattern of bits is also provided. The non-symmetric match circuit generates a non-symmetric match signal when the address matches the predetermined pattern. A hit signal generator that is coupled to the symmetric match circuit and a non-symmetric match circuit generates a hit signal which indicates whether or not the current address is stored in the cache memory.