Abstract: A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively connect the plurality of RAMs to the data operation processing section thereby changing the memory capacity allotted to each image formation operation among a plurality of image formation operations.

Abstract: An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Abstract: An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Abstract: An image processor has a transfer control section that transfers a sequence of image processing and data for image processing to be added or updated from a host buffer to program RAM and data RAM. The host buffer receives the sequence of image processing and data for image processing to be added or updated transferred from a process controller, and temporarily stores the sequence and the data during idle cycle time that a processor array section does not execute image processing. The transfer control section provides controls for transfer so that the sequence of image processing and data for image processing to be added or updated are split into blocks for a plurality of transfer times, and the blocks are transferred from the host buffer to the program RAM and the data RAM.

Abstract: An image processing apparatus efficiently removes an isolated point. A pixel area comprising a matrix area and a line area extending from the matrix area is defined. The matrix area includes a plurality of pixels forming a matrix so that a center pixel which is being processed is located in the center of the matrix. The line area includes a predetermined number of pixels along a scan line in which the center pixel is included so that the predetermined number of pixels extend from the matrix area. The center pixel is subjected to an isolated point removing process by referring to the pixels included in the pixel area.

Abstract: In the image processing apparatus a matrix selector selects a position matrix for determining the gradation direction. The gradation direction is the direction of a contrast of a gradation at a position of a target pixel and a dispersion matrix for determining a spatial frequency at the position of the target pixel. Further, a pixel interpolator divides the target pixel into still smaller pixels. A table selector selects a conversion table for determining a gradation level of the smaller pixels based on the gradation level of the target pixel, the position matrix and the dispersion matrix.

Abstract: The image processing device comprises a first function block section formed of functional blocks which require a supply of power so as to maintain the image processing device in an operating state when the power supply is on, and a second function block section formed of functional blocks which need not be supplied with the power so as to maintain the image processing device in an operating state even when the power supply is on. The supply of power to the second function block section can be stopped when desired, while continuing the supply of power to the first function block section, thereby saving the power.

Abstract: The image processing device comprises a first function block section formed of functional blocks which require a supply of power so as to maintain the image processing device in an operating state when the power supply is on, and a second function block section formed of functional blocks which need not be supplied with the power so as to maintain the image processing device in an operating state even when the power supply is on. The supply of power to the second function block section can be stopped when desired, while continuing the supply of power to the first function block section, thereby saving the power.

Abstract: The present invention relates to a polymer gel composition including: a swelling liquid; and a polymer gel having characteristics of absorbing and releasing the swelling liquid due to a change in temperature to thereby change a volume thereof reversibly, and including a crosslinked polymer having at least a hydrogen bonding group, wherein the crosslinked polymer included in the polymer gel is a copolymer of at least two monomer components including a (meth)acrylamide or a mono-substituted derivative thereof as a monomer component (A) and a monomer different from the monomer component (A) as a monomer component (B). The invention also relates to an optical device, a resin composition and an optical film, all using the polymer gel composition.

Abstract: An apparatus for forming an image that can stably provide an image for a long period of time is provided by using an electrophotographic photoreceptor having, as the outermost layer, a hard film containing one or more of a charge transporting organic silicon compound.

Abstract: The present invention relates to a manufacturing method of an electronic device comprising the steps of: preparing at least two kinds of hydrolytic silicon compounds that are different in reactivity to water; preparing a protective group precursor having a substituent having a reactivity to water equal or substantially equal to the reactivity of a reactive group of one of the hydrolytic silicon compounds to water; exchanging a reactive group of the other hydrolytic silicon compound with the substituent of the protective group precursor; preparing a silicon-containing coating agent containing the one of the hydrolytic silicon compounds and a hydrolytic silicon compound having the reactive group which has been exchanged with the substituent of the protective group precursor; and coating and curing the silicon-containing coating agent on a base plate so that at least one layer of a cured film is formed.

Abstract: In an image-processing apparatus, a digital image signal is stored in a memory, and a memory access control part entirely manages all accesses to the memory with respect to the digital image signal. An image processing part converts the digital image signal stored in the memory into an output image signal to be supplied to an imaging unit outputting a visible image based on the output image signal so that a pixel density of the output image signal is higher than a pixel density of the digital image signal read from the memory and an amount of the output image signal is less than an amount of the digital image signal stored in the memory. Accordingly, the central controlled memory is shared by a plurality of functions so as to effectively use the memory, and a high-quality image can be produced by carrying out a density conversion so as to match the pixel density.

Abstract: An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Abstract: The image processor comprises a switch that divides image data into m×n pixels, having n lines with m pixels per one line; a group of line memories that store the divided image; a compression device which batch compresses the image data of m×n pixels. Further, a command control unit provides control so as to send the (n−1) lines of image data among m×n pixels of image data to the group of line memories, and the remaining one line of image data directly to the compression device 902, and to send the m×(n−1) pixels of image data stored in the line memories to the compression device.

Abstract: A SIMD type processor includes a SIMD type arithmetic processing section which performs parallel processing by using a plurality of ALUs; and a global processor 102 that provides data to be arithmetically processed to a register and a data register group and provides the same instruction to each of the ALUs. Upon input of an interruption request for carrying out other parallel processing by interrupting a parallel processing currently carried out by the SIMD type arithmetic processing section, the global processor decides if the other parallel processing requested by the interruption request is to be carried out. The global processor suspends the parallel processing currently being carried out, when necessary. Then, the global processor provides data to be arithmetically processed by the interruption processing to the register and the data register group, and provides the same instruction necessary for carrying out the interruption processing to each of the ALUs.

Abstract: To solve problems associated with undesirable duplication of see-through back image in a double-sided input document, a method of and a system for substantially eliminating the undesirable see-through back images initially scanns a front side image and a back side image from the double-sided document and store the scanned images. The front side image has portions, and some of the portions include an original front image as well as a see-through back image from the back side image. An edge amount for each of the portions is determined in the front side image. The see-through back images are separated from the original front images based upon the edge amount. To further improve the correct removal of the undesired see-through back image, the above processed portions having a certain edge are smoothed. Character portions and dot pattern portions are further separated from background portions in the smoothed data.

Abstract: The image processing apparatus is provided with a plural memory controllers, each of which controls a RAM. The memory controllers are connected to an SIMD type arithmetic processing section. A control register is connected to the memory controllers. The control register controls transfer of image data between the RAMs and the SIMD type arithmetic processing section.

Abstract: The image processing apparatus comprises a reading unit which simultaneously reads image data from two, an obverse and a reverse, surfaces of a document, and a compressing unit which compresses received image data. The apparatus further comprises a controlling unit which orchestrates a flow of image data from the reading unit to the compressing unit in such a manner that the image data corresponding to the obverse surface and the reverse surface is input into the compressing unit at different timing.

Abstract: The image processing apparatus comprises an image data control section and a system controller. The image data control section is connected to any one or more of a sensor board unit, an image-memory access control section, an image processor, a video data control section, and a facsimile control unit. The system controller switches, when the image data to be transmitted to the image data control section conflicts with one another, a transmission mode of the image data in conflict with one another. Further, the image-memory access control section and the image processor share jobs of performing image processing on the image data.

Abstract: A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively connect the plurality of RAMs to the data operation processing section thereby changing the memory capacity allotted to each image formation operation among a plurality of image formation operations.