Patents by Inventor Rie Matsuo

Rie Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data slicer for generating a reference voltage
    Patent number: 7463309
    Abstract: A data slicer of the present invention comprises a reference voltage generation circuit and a comparator. The reference voltage generation circuit comprises a plurality of capacitances which area connected in parallel to one another, holding electrical charges on the basis of an input signal, a plurality of first switches which are connected to the plurality of capacitances with first nodes, respectively, for controlling the inflow of the input signal to the plurality of capacitances and a plurality of second switches which are connected to the plurality of capacitances with the first nodes, respectively, for controlling the connection among the plurality of capacitances. The plurality of first switches are controlled with predetermined timing where these first switches are individually brought into an ON state, and the plurality of second switches are controlled with predetermined timing where all the second switches are brought into an ON state.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: December 9, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Rie Matsuo, Kazuo Nomura
  • Data slicer
    Publication number: 20050212962
    Abstract: A data slicer of the present invention comprises a reference voltage generation circuit and a comparator. The reference voltage generation circuit comprises a plurality of capacitances which area connected in parallel to one another, holding electrical charges on the basis of an input signal, a plurality of first switches which are connected to the plurality of capacitances with first nodes, respectively, for controlling the inflow of the input signal to the plurality of capacitances and a plurality of second switches which are connected to the plurality of capacitances with the first nodes, respectively, for controlling the connection among the plurality of capacitances. The plurality of first switches are controlled with predetermined timing where these first switches are individually brought into an ON state, and the plurality of second switches are controlled with predetermined timing where all the second switches are brought into an ON state.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 29, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Rie Matsuo, Kazuo Nomura