Patents by Inventor Rie MIZUTANI
Rie MIZUTANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11792927Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.Type: GrantFiled: August 4, 2022Date of Patent: October 17, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Rie Mizutani, Noriyoshi Shimizu, Hiroshi Taneda, Masaya Takizawa, Yoshiki Akiyama
-
Patent number: 11729914Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.Type: GrantFiled: April 26, 2022Date of Patent: August 15, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO.. LTD.Inventors: Hiroshi Taneda, Noriyoshi Shimizu, Rie Mizutani, Masaya Takizawa, Yoshiki Akiyama
-
Patent number: 11716810Abstract: A wiring board includes a first interconnect structure including a first interconnect layer, and a first insulating layer including a non-photosensitive thermosetting resin as a main component thereof, a second interconnect structure including second interconnect layers, and second insulating layers including a photosensitive resin as a main component thereof, and laminated on the first interconnect structure, and an encapsulating resin layer including a non-photosensitive thermosetting resin as a main component thereof, and laminated on an uppermost second insulating layer. An uppermost second interconnect layer includes a pad protruding from the uppermost second insulating layer. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad. Thermal expansion coefficients of the first insulating layer and the encapsulating resin layer are lower than that of the second insulating layers.Type: GrantFiled: April 26, 2022Date of Patent: August 1, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Masaya Takizawa, Rie Mizutani, Hiroshi Taneda, Yoshiki Akiyama, Noriyoshi Shimizu
-
Publication number: 20230066839Abstract: A wiring board includes an interconnect structure including a plurality of interconnect layers, and a plurality of insulating layers having a photosensitive resin as a main component thereof, and an encapsulating resin layer having a non-photosensitive thermosetting resin as a main component thereof, laminated on an uppermost insulating layer of the plurality of insulating layers. An uppermost interconnect layer of the plurality of interconnect layers includes a pad protruding from the uppermost insulating layer. The encapsulating resin layer exposes an upper surface of the pad, and covers at least a portion of a side surface of the pad, and at least a portion of side surfaces of the plurality of insulating layers. The pad is configured to receive a semiconductor chip to be mounted thereon.Type: ApplicationFiled: August 3, 2022Publication date: March 2, 2023Inventors: Hiroshi TANEDA, Noriyoshi SHIMIZU, Rie MIZUTANI, Masaya TAKIZAWA, Yoshiki AKIYAMA
-
Publication number: 20230054390Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.Type: ApplicationFiled: August 4, 2022Publication date: February 23, 2023Inventors: Rie MIZUTANI, Noriyoshi SHIMIZU, Hiroshi TANEDA, Masaya TAKIZAWA, Yoshiki AKIYAMA
-
Publication number: 20220361340Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.Type: ApplicationFiled: April 26, 2022Publication date: November 10, 2022Inventors: Hiroshi TANEDA, Noriyoshi SHIMIZU, Rie MIZUTANI, Masaya TAKIZAWA, Yoshiki AKIYAMA
-
Publication number: 20220361331Abstract: A wiring board includes a first interconnect structure including a first interconnect layer, and a first insulating layer including a non-photosensitive thermosetting resin as a main component thereof, a second interconnect structure including second interconnect layers, and second insulating layers including a photosensitive resin as a main component thereof, and laminated on the first interconnect structure, and an encapsulating resin layer including a non-photosensitive thermosetting resin as a main component thereof, and laminated on an uppermost second insulating layer. An uppermost second interconnect layer includes a pad protruding from the uppermost second insulating layer. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad. Thermal expansion coefficients of the first insulating layer and the encapsulating resin layer are lower than that of the second insulating layers.Type: ApplicationFiled: April 26, 2022Publication date: November 10, 2022Inventors: Masaya TAKIZAWA, Rie MIZUTANI, Hiroshi TANEDA, Yoshiki AKIYAMA, Noriyoshi SHIMIZU
-
Patent number: 10804210Abstract: A wiring board includes an insulating layer, and a metal layer, formed on the insulating layer, and including a first pattern that includes a plurality of wirings extending parallel to each other, and a second pattern that includes a degassing hole. The insulating layer includes a groove exposed between the plurality of wirings, and a surface of the insulating layer inside the degassing hole is located above a bottom surface of the groove.Type: GrantFiled: December 11, 2019Date of Patent: October 13, 2020Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Rie Mizutani
-
Patent number: 10743403Abstract: A wiring board includes an insulating layer, and a metal layer. The insulating layer includes a first pattern and a second pattern. The first pattern includes first grooves extending parallel to each other, and a first projecting part separating adjacent first grooves. The second pattern includes a second projecting part, and a second groove surrounding the second projecting part. The metal layer includes a wiring formed within the first grooves, and a degassing hole formed within the second pattern and having an opening formed by the second projecting part.Type: GrantFiled: December 16, 2019Date of Patent: August 11, 2020Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Rie Mizutani
-
Publication number: 20200214122Abstract: A wiring board includes an insulating layer, and a metal layer. The insulating layer includes a first pattern and a second pattern. The first pattern includes first grooves extending parallel to each other, and a first projecting part separating adjacent first grooves. The second pattern includes a second projecting part, and a second groove surrounding the second projecting part. The metal layer includes a wiring formed within the first grooves, and a degassing hole formed within the second pattern and having an opening formed by the second projecting part.Type: ApplicationFiled: December 16, 2019Publication date: July 2, 2020Inventor: Rie MIZUTANI
-
Publication number: 20200211971Abstract: A wiring board includes an insulating layer, and a metal layer, formed on the insulating layer, and including a first pattern that includes a plurality of wirings extending parallel to each other, and a second pattern that includes a degassing hole. The insulating layer includes a groove exposed between the plurality of wirings, and a surface of the insulating layer inside the degassing hole is located above a bottom surface of the groove.Type: ApplicationFiled: December 11, 2019Publication date: July 2, 2020Inventor: Rie MIZUTANI