Patents by Inventor Rieko Suzuki

Rieko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Anti-canine TARC antibody used for treatment and diagnosis of canine atopic dermatitis
    Patent number: 11104727
    Abstract: Provided are an anti-canine TARC antibody for use in the treatment and diagnosis of canine atopic dermatitis, and a method for treating or diagnosing canine atopic dermatitis using the same. An anti-canine TARC monoclonal antibody binding to canine TARC, comprising a heavy chain variable region consisting of the amino acid sequence shown in SEQ ID NO: 2 and a light chain variable region consisting of the amino acid sequence shown in SEQ ID NO: 4, or a functional fragment thereof binding to canine TARC.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 31, 2021
    Assignee: NIPPON ZENYAKU KOGYO CO., LTD.
    Inventors: Toshihiro Tsukui, Miyuki Kageyama, Masahiro Kato, Rieko Suzuki
  • ANTI-CANINE TARC ANTIBODY USED FOR TREATMENT AND DIAGNOSIS OF CANINE ATOPIC DERMATITIS
    Publication number: 20180319879
    Abstract: Provided are an anti-canine TARC antibody for use in the treatment and diagnosis of canine atopic dermatitis, and a method for treating or diagnosing canine atopic dermatitis using the same. An anti-canine TARC monoclonal antibody binding to canine TARC, comprising a heavy chain variable region consisting of the amino acid sequence shown in SEQ ID NO: 2 and a light chain variable region consisting of the amino acid sequence shown in SEQ ID NO: 4, or a functional fragment thereof binding to canine TARC.
    Type: Application
    Filed: October 13, 2016
    Publication date: November 8, 2018
    Applicant: NIPPON ZENYAKU KOGYO CO., LTD.
    Inventors: Toshihiro TSUKUI, Miyuki KAGEYAMA, Masahiro KATO, Rieko SUZUKI
  • Method and apparatus for calculating delay times in semiconductor circuit
    Patent number: 6389381
    Abstract: A method and apparatus for calculating circuit delay times efficiently arranges and stores data to reduce system memory requirements, which allows computers without large storage devices, such as conventional personal computers with limited hard disk space, to be used for testing preliminary device designs, Delay time ratio coefficient values representing a ratio of a delay time determined by values of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element are stored in a coefficient table. The dependency factors include process condition, in use or operational temperature, and first and second operational supply voltages.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: May 14, 2002
    Assignee: Fujitsu Limited
    Inventors: Masahito Isoda, Takashi Yoneda, Rieko Suzuki
  • Manufacturing method and apparatus of a semiconductor integrated circuit device
    Patent number: 6035111
    Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: March 7, 2000
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Rieko Suzuki, Kiyoshi Saida, Kazushige Itazu, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida, Takako Murakami, Teruhisa Tsuyuki, Kazunori Kawazoe, Takeshi Shimazaki, Yukimi Nishiwaki
  • Manufacturing method and apparatus of a semiconductor integrated circuit device
    Patent number: 5618744
    Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: April 8, 1997
    Assignees: Fujitsu Ltd., Fujitsu VLSI Ltd.
    Inventors: Rieko Suzuki, Kiyoshi Saida, Kazushige Itazu, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida, Takako Murakami, Teruhisa Tsuyuki, Kazunori Kawazoe, Takeshi Shimazaki, Yukimi Nishiwaki