Abstract: A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.

Abstract: An integrated circuit chip includes at least one driver circuit of single-ended structure and the first drive circuit, the first drive circuit and the at least one driver circuit of single-ended structure have the same structure, the first drive circuit includes a plurality of parallel-connected PMOS tubes and a plurality of parallel-connected NMOS tubes, the plurality of parallel-connected PMOS tubes connect the plurality of parallel-connected NMOS tube in series at a first node. After impedance calibration has been conducted, the chip confines a first impedance calibration code and a second impedance calibration code, and controls the at least one driver according to the first impedance calibration code and the second impedance calibration code; the first reference voltage is preferably configured to ¾ times of the supply voltage VDD, and the second reference voltage is preferably configured to ¼ times of the supply voltage VDD.

Abstract: An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

Abstract: A charge pump circuit includes a first PMOS transistor and a first NMOS transistor that are connected in series to a main charging and discharging circuit, where a grid electrode of the first PMOS transistor is controlled by an inverted signal of a first control signal. A grid electrode of the first NMOS transistor is controlled by a second control signal. The circuit further includes a second PMOS transistor that is located in a first branch circuit, where a grid electrode of the second PMOS transistor is controlled by the first control signal; and includes a second NMOS transistor that is located in a second branch circuit, where a grid electrode of the second NMOS transistor is controlled by an inverted signal of the second control signal. The embodiments resolve a problem of leakage currents.

Abstract: A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.

Abstract: A power-on reset (POR) circuit includes an RC circuit; a Schmitt trigger, an inverter, and a first PMOS tube. A power supply voltage charges a capacitor through the RC circuit. When a voltage of the capacitor reaches a first threshold, the Schmitt trigger reverses, a first level is output. The POR circuit includes a discharge circuit used to detect a glitch of the power supply voltage, and output a first signal to an input end of the Schmitt trigger when the glitch is detected. The first signal allows the Schmitt trigger to reverse again to output a second level, so as to turn off the first PMOS tube through the inverting amplifier. When the power supply voltage rises along an oblique line again, the Schmitt trigger reverses, and the first level is output, so as to reset the system where the circuit is.

Abstract: An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

Abstract: An integrated circuit chip includes at least one driver circuit of single-ended structure and the first drive circuit, the first drive circuit and the at least one driver circuit of single-ended structure have the same structure, the first drive circuit includes a plurality of parallel-connected PMOS tubes and a plurality of parallel-connected NMOS tubes, the plurality of parallel-connected PMOS tubes connect the plurality of parallel-connected NMOS tube in series at a first node. After impedance calibration has been conducted, the chip confines a first impedance calibration code and a second impedance calibration code, and controls the at least one driver according to the first impedance calibration code and the second impedance calibration code; the first reference voltage is preferably configured to 3/4 times of the supply voltage VDD,and the second reference voltage is preferably configured to 1/4 times of the supply voltage VDD.

Abstract: A power-on reset (POR) circuit includes an RC circuit; a Schmitt trigger, an inverter, and a first PMOS tube. A power supply voltage charges a capacitor through the RC circuit. When a voltage of the capacitor reaches a first threshold, the Schmitt trigger reverses, a first level is output. The POR circuit includes a discharge circuit used to detect a glitch of the power supply voltage, and output a first signal to an input end of the Schmitt trigger when the glitch is detected. The first signal allows the Schmitt trigger to reverse again to output a second level, so as to turn off the first PMOS tube through the inverting amplifier. When the power supply voltage rises along an oblique line again, the Schmitt trigger reverses, and the first level is output, so as to reset the system where the circuit is.

Abstract: Embodiments of the present invention disclose a level up shifter circuit. The level up shifter circuit further includes two field effect transistors connected in series and a control circuit. Sources of the two field effect transistors and a source of a sixth field effect transistor are respectively connected to a drain of a first field effect transistor and a drain of a second field effect transistor of the conversion circuit, and the control circuit is turned on when a first voltage signal and a third voltage signal are zero at the same time and is turned off in other situations. The level up shifter circuit according to the embodiments of the present invention can effectively solve the problem that an output state is unknown.

Abstract: A crystal oscillator circuit includes: a crystal resonator circuit, generating an oscillation signal; an inverting amplification circuit, whose amplifier input end is coupled to receive the oscillation signal, in which an inverting amplifier outputs an inverting amplified output signal; a bias circuit, having a bias circuit input end and a bias circuit output end, in which the bias circuit output end generates a bias circuit output signal controlled by the bias circuit input end, and the bias circuit output signal is coupled to a second control end of the inverting amplification circuit; and a peak detection circuit, comparing the inverting amplified output signal with a reference signal, regulating a peak detector output signal, and feeding the peak detector output signal into the bias circuit input end.

Abstract: A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency.

Abstract: Embodiments of the present invention disclose a level up shifter circuit. The level up shifter circuit further includes two field effect transistors connected in series and a control circuit. Sources of the two field effect transistors and a source of a sixth field effect transistor are respectively connected to a drain of a first field effect transistor and a drain of a second field effect transistor of the conversion circuit, and the control circuit is turned on when a first voltage signal and a third voltage signal are zero at the same time and is turned off in other situations. The level up shifter circuit according to the embodiments of the present invention can effectively solve the problem that an output state is unknown.

Abstract: A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency.

Abstract: A crystal oscillator circuit includes: a crystal resonator circuit, generating an oscillation signal; an inverting amplification circuit, whose first amplifier input end is coupled to receive the oscillation signal, in which an inverting amplifier outputs an inverting amplified output signal; a bias circuit, having a bias circuit input end and a bias circuit output end, in which the bias circuit output end generates a bias circuit output signal controlled by the bias circuit input end, and the bias circuit output signal is coupled to a second amplifier input end; and a peak detection circuit, comparing the inverting amplified output signal with a reference signal, regulating a peak detector output signal, and feeding the peak detector output signal into the bias circuit input end, in which the bias circuit includes a self-adjusting circuit, for isolating a power supply from a second input end of the inverting amplifier.

Abstract: A delay circuit is described having a variable capacitor and a triggering circuit. The variable capacitor and the triggering circuit may both include transistors. With both the variable capacitor and the triggering circuit dependent on the threshold voltage, the delay circuit may be less sensitive to process variations. The delay circuit may also include a capacitor, a first triggering circuit, a second triggering circuit, and a pull down circuit. The capacitor may discharge at a first rate, triggering the first triggering circuit which, in turn, activates the pull down circuit to pull down the capacitor at a second rate that is faster than the first rate. The second triggering circuit is triggered as the capacitor is pulled down, thereby reducing the effect of input signal noise on the output of the delay circuit. The discharging of the capacitor may be adjusted by a control input thereby making the delay of the delay circuit programmable.

Abstract: A delay circuit is described having a variable capacitor and a triggering circuit. The variable capacitor and the triggering circuit may both comprise transistors. With both the variable capacitor and the triggering circuit dependent on the threshold voltage, the delay circuit may be less sensitive to process variations. The delay circuit may also include a capacitor, a first triggering circuit, a second triggering circuit, and a pull down circuit. The capacitor may discharge at a first rate, triggering the first triggering circuit which, in turn, activates the pull down circuit to pull down the capacitor at a second rate that is faster than the first rate. The second triggering circuit is triggered as the capacitor is pulled down, thereby reducing the effect of input signal noise on the output of the delay circuit. The discharging of the capacitor may be adjusted by a control input thereby making the delay of the delay circuit programmable.

Abstract: A sigma-delta modulated analog-to-digital converter having an integrator with a first changeable coefficient and/or having an excess loop-delay circuit also having a second changeable coefficient. The changeable coefficients enable the converter to account for noise mixed with the input signal, circuit non-linearities, and component variations.

Abstract: Tone-free dithering methods for sigma-delta digital-to-analog converters are disclosed. A dither signal having a frequency outside of the baseband frequency of a converter is provided to randomize the baseband noise floor of the converter such that there is no idle tone existing in the useful frequency range. In practice, the dither signal is combined with the input signal at the front end of a sigma-delta modulator. The dither signal may be a sinusoidal waveform (or other types of waveforms) and/or a DC level at a frequency outside of the baseband frequency range of the converter. The dither signal may be combined with the input signal either before or after an interpolator. The out of band dither signal breaks up the idle tones and does not affect the dynamic range of the converter. It can be used in a wide variety of applications requiring high fidelity and stability.