Abstract: A memory device and an operating method of a memory controller are described in which the operating method includes determining that a NOT operation for data of a cell is to be performed by the memory device; forming, in a bit line connected to the cell, a reference voltage between a first voltage corresponding to the data and a second voltage corresponding to inversion data of the data; forming, in the bit line, a third voltage between the second voltage and the reference voltage by connecting the bit line and a bit line bar; forming the reference voltage in the bit line bar; and sensing the inversion data based on the third voltage formed in the bit line and the reference voltage formed in the bit line bar, wherein the inversion data comprises an output of the NOT operation for the data of the cell.

Abstract: A method and apparatus are provided. The method includes reordering a plurality of filters, then based on a result of the reordering, compressing weights, among a plurality of weights of the plurality of filters, resulting in some of the plurality of weights being uncompressed weights, generating a plurality of operation unit maps by mapping the uncompressed weights to respective operation units according to a predetermined bulk unit, and mapping the plurality of operation unit maps to an array.