Patents by Inventor Rihito Kuroda

Rihito Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8362567
    Abstract: In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10?11 ?cm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: January 29, 2013
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Publication number: 20120146102
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 14, 2012
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Patent number: 8138527
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: March 20, 2012
    Assignees: National University Corporation Tohoku University, Foundation For Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Publication number: 20110042725
    Abstract: With inversion-mode transistors, intrinsic-mode transistors, or semiconductor-layer accumulation-layer current controlled accumulation-mode transistors, variation in threshold voltages becomes large in miniaturized generations due to statistical variation in impurity atom concentrations and thus it is difficult to maintain the reliability of an LSI. Provided is a bulk current controlled accumulation-mode transistor which is formed by controlling the thickness and the impurity atom concentration of a semiconductor layer so that the thickness of a depletion layer becomes greater than that of the semiconductor layer. For example, by setting the thickness of the semiconductor layer to 100 nm and setting the impurity concentration thereof to be higher than 2×1017 [cm?3], the standard deviation of variation in threshold values can be made smaller than a power supply voltage-based allowable variation value.
    Type: Application
    Filed: April 10, 2009
    Publication date: February 24, 2011
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Publication number: 20100213516
    Abstract: On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).
    Type: Application
    Filed: October 6, 2008
    Publication date: August 26, 2010
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Tomoyuki Suwa, Rihito Kuroda, Hideo Kudo, Yoshinori Hayamizu
  • Publication number: 20100059830
    Abstract: In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10?11 ?cm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
    Type: Application
    Filed: July 12, 2007
    Publication date: March 11, 2010
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Publication number: 20090309138
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Application
    Filed: July 12, 2007
    Publication date: December 17, 2009
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda