Abstract: A TFT in which a channel region is formed of an oxide semiconductor is provided. Threshold voltage shift due to holes photoexcited in the vicinity of a source electrode and a drain electrode is prevented so that reliability is enhanced. A lower semiconductor layer is partially provided between an oxide semiconductor layer and a gate insulating film. The lower semiconductor layer is present in at least one of a source overlapping region where the oxide semiconductor layer overlaps a source electrode and a drain overlapping region where the oxide semiconductor layer overlaps a drain electrode. In contrast, a region where the lower semiconductor layer is absent is provided between the source overlapping region and the drain overlapping region.

Abstract: It is an object of the present invention to provide a technique capable of reducing a contact resistance between source and drain electrodes and a channel region. A thin film transistor includes: a first semiconductor layer provided on a first insulation film lying on a gate electrode and adjacent to a partial region that is part of the first insulation film lying on the gate electrode as seen in plan view; a source electrode and a drain electrode sandwiching the partial region therebetween as seen in plan view; a second insulation film having an opening portion provided over the partial region; and a second semiconductor layer provided on the second insulation film. The second semiconductor layer is in contact with the source electrode and the drain electrode, and is in contact with the partial region and the first semiconductor layer through the opening portion of the second insulation film.

Abstract: It is an object of the present invention to provide a technique capable of reducing a contact resistance between source and drain electrodes and a channel region. A thin film transistor includes: a first semiconductor layer provided on a first insulation film lying on a gate electrode and adjacent to a partial region that is part of the first insulation film lying on the gate electrode as seen in plan view; a source electrode and a drain electrode sandwiching the partial region therebetween as seen in plan view; a second insulation film having an opening portion provided over the partial region; and a second semiconductor layer provided on the second insulation film. The second semiconductor layer is in contact with the source electrode and the drain electrode, and is in contact with the partial region and the first semiconductor layer through the opening portion of the second insulation film.

Abstract: A TFT in which a channel region is formed of an oxide semiconductor is provided. Threshold voltage shift due to holes photoexcited in the vicinity of a source electrode and a drain electrode is prevented so that reliability is enhanced. A lower semiconductor layer is partially provided between an oxide semiconductor layer and a gate insulating film. The lower semiconductor layer is present in at least one of a source overlapping region where the oxide semiconductor layer overlaps a source electrode and a drain overlapping region where the oxide semiconductor layer overlaps a drain electrode. In contrast, a region where the lower semiconductor layer is absent is provided between the source overlapping region and the drain overlapping region.

Abstract: The present technique relates to a transistor that uses an oxide semiconductor as its channel layer and that is capable of suppressing fluctuations in threshold voltage, and to a thin-film transistor substrate and a liquid crystal display that include such a transistor. The transistor is configured such that an overlap length, which is a length of overlap in plan view between the source electrode and the channel protective film in a direction from the source electrode toward the drain electrode, is longer than an overlap length, which is a length of overlap in plan view between the drain electrode and the channel protective film in a direction from the drain electrode toward the source electrode.

Abstract: The present technique relates to a transistor that uses an oxide semiconductor as its channel layer and that is capable of suppressing fluctuations in threshold voltage, and to a thin-film transistor substrate and a liquid crystal display that include such a transistor. The transistor is configured such that an overlap length, which is a length of overlap in plan view between the source electrode and the channel protective film in a direction from the source electrode toward the drain electrode, is longer than an overlap length, which is a length of overlap in plan view between the drain electrode and the channel protective film in a direction from the drain electrode toward the source electrode.

Abstract: A thin-film transistor substrate constituting a liquid crystal display includes: a thin-film transistor including, a gate electrode, a gate insulating film covering the gate electrode, a semiconductor layer opposing the gate electrode via the gate insulating film, a channel protective film covering the semiconductor layer, a protective film covering over the channel protective film, source and drain electrodes in contact with the semiconductor layer through first contact holes penetrating through the protective film and the channel protective film; a first electrode electrically connected to the drain electrode; a gate wiring extending from the gate electrode; and a source wiring electrically connected to the source electrode. The source wiring and first electrode are respectively electrically connected to the source electrode and drain electrode through respective second contact holes penetrating through the protective film.

Abstract: A thin-film transistor substrate constituting a liquid crystal display includes: a thin-film transistor including, a gate electrode, a gate insulating film covering the gate electrode, a semiconductor layer opposing the gate electrode via the gate insulating film, a channel protective film covering the semiconductor layer, a protective film covering over the channel protective film, source and drain electrodes in contact with the semiconductor layer through first contact holes penetrating through the protective film and the channel protective film; a first electrode electrically connected to the drain electrode; a gate wiring extending from the gate electrode; and a source wiring electrically connected to the source electrode. The source wiring and first electrode are respectively electrically connected to the source electrode and drain electrode through respective second contact holes penetrating through the protective film.