Patents by Inventor Riichiro TAKAISHI
Riichiro TAKAISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10367054Abstract: A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.Type: GrantFiled: September 8, 2017Date of Patent: July 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hidenori Miyagawa, Riichiro Takaishi, Toshinori Numata
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Patent number: 10249818Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.Type: GrantFiled: March 6, 2018Date of Patent: April 2, 2019Assignee: Toshiba Memory CorporationInventors: Marina Yamaguchi, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
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Publication number: 20190088870Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.Type: ApplicationFiled: March 6, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Marina YAMAGUCHI, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
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Publication number: 20180269277Abstract: A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.Type: ApplicationFiled: September 8, 2017Publication date: September 20, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hidenori MIYAGAWA, Riichiro TAKAISHI, Toshinori NUMATA
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Patent number: 9691973Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.Type: GrantFiled: September 2, 2015Date of Patent: June 27, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Riichiro Takaishi, Koichi Kato, Yasushi Nakasaki, Takamitsu Ishihara, Daisuke Matsushita
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Patent number: 9530855Abstract: This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film.Type: GrantFiled: July 7, 2015Date of Patent: December 27, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masamichi Suzuki, Yusuke Higashi, Riichiro Takaishi, Mitsuhiro Tomita, Kiwamu Sakuma, Yuichiro Mitani
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Publication number: 20160079434Abstract: This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film.Type: ApplicationFiled: July 7, 2015Publication date: March 17, 2016Inventors: Masamichi SUZUKI, Yusuke HIGASHI, Riichiro TAKAISHI, Mitsuhiro TOMITA, Kiwamu SAKUMA, Yuichiro MITANI
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Publication number: 20150380641Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.Type: ApplicationFiled: September 2, 2015Publication date: December 31, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Riichiro Takaishi, Koichi Kato, Yasushi Nakasaki, Takamitsu Ishihara, Daisuke Matsushita
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Patent number: 9190615Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: GrantFiled: August 14, 2014Date of Patent: November 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Takaishi, Hidenori Miyagawa, Shosuke Fujii
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Publication number: 20140353572Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: ApplicationFiled: August 14, 2014Publication date: December 4, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Riichiro Takaishi, Hidenori Miyagawa, Shosuke Fujii
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Patent number: 8860182Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: GrantFiled: September 6, 2013Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Takaishi, Hidenori Miyagawa, Shosuke Fujii
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Publication number: 20140284541Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.Type: ApplicationFiled: September 6, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Riichiro TAKAISHI, Hidenori Miyagawa, Shosuke Fujii