Patents by Inventor Riju Biswas

Riju Biswas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979264
    Abstract: Methods and systems are provided for processing a signal over a serial link. The methods and systems receive, by an adjustable filter, a serial input signal, the adjustable filter configured to set a corner frequency of a channel response and a gain of the channel response, the adjustable filter adding a zero to the channel response before to a pole of the serial input signal. The methods and systems selectively apply, by a bandwidth booster component, compensation to signal attenuation of the serial input signal in a first mode of operation and of one or more test signals in a second mode of operation of a serial link receiver. The methods and systems generate, by one or more continuous time linear equalizers configured to receive on an output of the bandwidth booster, one or more output signals of the receiver based on an output signal from the bandwidth booster component.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: May 7, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Riju Biswas, Abhishek Shrivastava
  • Patent number: 11777491
    Abstract: Various embodiments provide for a continuous time linear equalizer (CTLE) that includes an active inductor, which can be included in a receiver portion of a circuit. For some embodiments, the CTLE in combination with the active inductor can implement a signal transfer function comprising at least two zeros and two poles.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: October 3, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventor: Riju Biswas
  • Patent number: 11757458
    Abstract: In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: September 12, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vineeth Anavangot, Riju Biswas
  • Patent number: 11658624
    Abstract: Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Riju Biswas, Ratul Mitra
  • Publication number: 20220407481
    Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 22, 2022
    Inventor: Riju Biswas
  • Patent number: 11502659
    Abstract: Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: November 15, 2022
    Assignee: STMicroelectronics International N.V.
    Inventor: Riju Biswas
  • Patent number: 11444580
    Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: September 13, 2022
    Assignee: STMicroelectronics International N.V.
    Inventor: Riju Biswas
  • Patent number: 11381207
    Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics International N.V.
    Inventor: Riju Biswas
  • Publication number: 20210399705
    Abstract: Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 23, 2021
    Applicant: STMicroelectronics International N.V.
    Inventor: Riju BISWAS
  • Publication number: 20210391837
    Abstract: Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Applicant: STMicroelectronics International N.V.
    Inventors: Riju BISWAS, Ratul MITRA
  • Publication number: 20210313941
    Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 7, 2021
    Inventor: Riju Biswas
  • Publication number: 20210313933
    Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventor: Riju Biswas
  • Patent number: 11121687
    Abstract: Disclosed herein is a circuit including a differential amplifier having a pair of input transistors coupled in a differential arrangement between adjustable current sources and receiving input differential signals from a pair of input voltage regulators. The adjustable current sources are configured to source more current to the pair of input transistors than current that is sunk from the pair of input transistors. A first amplifier has inputs coupled to receive differential output voltages from the differential amplifier. A second amplifier has inputs coupled to receive amplified differential output voltages from the first amplifier. A low pass filter has inputs coupled to receive further amplified differential output voltages from the second amplifier and produce final differential output voltages.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Riju Biswas, Ratul Mitra