Abstract: An internal frame signal producing circuit for use in a cross connection system which cross connects first bit rate signals, each produced by multiplexing m second bit rate signals at first or the second bit rate signal levels, the first bit rate being higher than the second bit rate, an internal frame frequency is predetermined to be equal to a frequency f.sub.h ' higher than a first nominal frequency f.sub.h of the first bit rate digital signals by a predetermined value, the frequency f.sub.h ' being synchronized with a second nominal frequency fl of the second bit rate digital signals. In order to obtain the internal frame signal, from m second bit rate signals, the m second bit rate signals are stuff-synchronized processed to produce m stuff-synchronized signals, each having a stuff bit, a variable bit, and vacant bit at suitable bit intervals in a frame of a frame length. The m stuffed-synchronized signals are serially arranged to make the internal frame signal.

Abstract: In a cross-connection network, a plurality of asynchronous input digital signals can be cross-connected to a plurality of output lines by use of time switch. The input digital signals are pulse stuffed at a common higher bit rate and are synchronized to one another by attaching extra bits. The pulse stuffed signals are assigned into serial frames in a predetermined order by the multiplex technique and are interchanged from one to another by the time switch in the time division fashion. The frame-interchanged signal is demultiplexed to reproduce the pulse-stuffed signals which are sent out to the respective output lines assigned to the frames after removing extra bits. When the input digital signals are of higher order group, each of the higher order group digital signals is demultiplexed to lower order group signals which are pulse stuffed to be synchronized to the common higher bit rate.

Abstract: An A-D converter which oversamples the input analog signal, at a frequency greater than the Nyquist frequency, and achieves high precision linear coding by performing simple operations at a high sampling frequency f.sub.H while complicated operations are performed at a low sampling frequency f.sub.s. The high sampling frequency may be reduced to the low sampling frequency through a two-step reduction using a sampling frequency converter to reduce the frequency to an intermediate frequency f.sub.M and an integrator/sampler to reduce the sampling frequency further to f.sub.s or directly with the use of an FIR filter having a frequency characteristic in which attenuation is large in the out-of-band and gain deviation is small in-band.

Abstract: An adaptive differential pulse code modulated (ADPCM) transmission system includes a subtractor for providing a difference signal E.sub.j between an input signal X.sub.j and a predicted signal X.sub.j. A coder encodes the difference signal E.sub.j into a coded signal U.sub.j for transmission to a receiver. The signal U.sub.j is also decoded at the transmitter to produce a reproduced error signal E.sub.j. A prediction circuit operates to generate a prediction signal X.sub.j on the basis of the reproduced error signal E.sub.j. The prediction circuit is controlled by a control circuit which operates to detect transmitter instability. A first level detector in the control circuit compares the input signal level against the level of a transmitter produced signal representing the input signal. A second level detector of the control circuit determines when the input signal is below a specified value.

Abstract: A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment.

Abstract: A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment.

Abstract: A PCM signal interface apparatus comprises a buffer memory being capable of asynchronously writing and reading a PCM signal, means for inserting a frame marker to the PCM signal upon writing the PCM signal into the buffer memory, means for judging whether or not the frame marker is contained in an output signal read out of the buffer memory at a time that is designated by an external read frame position designating pulse, means for resetting all the contents in the buffer memory and temporarily stopping the supply of a writing clock and a reading clock to the buffer memory when the frame marker is not delivered out at the predetermined time, means for resuming the supply of the writing clock to the buffer memory by receiving a write frame position designating pulse, and means for resuming the supply of the reading clock to the buffer memory by receiving the frame position designating pulse at a predetermined time lapse after the resumption of the writing clock supply.

Abstract: An N-point DFT (discrete Fourier transform) calculator comprises a pre-processor responsive to N-point complex input data F.sub.k (k=0 to N-1) for producing N/2-point complex intermediate data G.sub.p (p=0 to N/2-1) and an N/2-point DFT calculating circuit supplied with the intermediate data as N/2-point complex input data for producing in a known manner real and imaginary parts g.sub.q.sup.R and g.sub.q.sup.I of DFT's or IDFT's (inverse DFT) g.sub.q (q=0 to N/2-1) of the latter input data G.sub.p as either real or imaginary parts f.sub.n.sup.R or f.sub.n.sup.I (n=0 to N-1) of even and odd numbered DFT's or IDFT's f.sub.2n' and f.sub.2n'+1 (n'=0 to N/2-1) of the original input data F.sub.k. The pre-processor extracts from the input data F.sub.k a truncated sequence of conjugate symmetric or antisymmetric components H.sub.m, N/2+1 in number, extracts from the truncated sequence conjugate symmetric and antisymmetric components A.sub.p and B.sub.

Abstract: An SSB-FDM modulator derived from a complex band-pass digital filter bank and by a filter breakdown process comprises a discrete Fourier transform (DFT) processor capable of giving phase offsets to complex output signals thereof. In a broader sense, DFT includes inverse DFT (IDFT). The processor is called an offset discrete Fourier transform (ODFT) processor and supplied with real baseband sample sequences. The phase offset complex output signals are frequency-selected by a complex band-pass digital filter unit operable at a sampling frequency for the baseband sample sequences into a real SSB-FDM signal. An SSB-FDM demodulator likewise derived comprises a complex band-pass digital filter unit for frequency-selecting a real SSB-FDM signal into complex sample sequences of the respective baseband channels. The complex sample sequences are ODFT'ed into real baseband sample sequences.

Abstract: An asynchronous PCM common decoding apparatus decodes asynchronous PCM signals sent from a plurality of transmitter sources. The apparatus includes a plurality of receiver units each of which generate a digital signal to be decoded, a channel-number-designating signal, and a decode-requesting signal. One or more decoders are provided to decode the digital signals from the receiver units to analog signals. The decoders produce status signals indicating availabilities of the decoders for decoding the digital signals. A common control unit is responsive to both the decode-requesting signals and the status signals to successively allot a combination of a given receiver and a given decoder.

Abstract: Method and apparatus for cancelling a deviation in an input signal due to drift, line or background noise, changes in circuit component characteristics due to aging, and the like wherein the input signal, typically a digitized representation of an analog signal, is altered by a presumed offset magnitude; the polarity of the difference is monitored and a negative or positive count of clock pulses is accumulated dependent upon the aforesaid polarity. When a determined positive (or negative) count is reached the presumed offset is adjusted (up or down) by a predetermined increment and the count is begun anew.As an alternative technique and embodiment the initiation of the count may be restrained as long as the magnitude of the digitized input signal exceeds a predetermined threshold.

Abstract: A PCM-TASI signal transmission system utilizes assignment control means responsive to an output signal from means for detecting the presence of information on each of a plurality (m) of input trunks arranged in time-serial fashion. The assignment control means selectively assigns a PCM signal representing the input trunk signal, during the period when information is present thereon, to one of a second plurality (s) of transmission channels (s<m). The assignment control means includes means for generating and transmitting signals representing the selected assignments state of the input trunks.