Patents by Inventor Rikio Sugiura

Rikio Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4984059
    Abstract: In a plastic molded semiconductor device in which inner leads overlap a semiconductor chip in a molded plastic body, the width of the chip may be close to the width of the plastic body without a decrease in the high resistance of the inner leads to the pull out thereof from the plastic body, and the layout of the inner leads may be unrestricted since the inner leads may occupy the region above the chip.
    Type: Grant
    Filed: October 7, 1983
    Date of Patent: January 8, 1991
    Assignee: Fujitsu Limited
    Inventors: Akihiro Kubota, Rikio Sugiura, Tsuyoshi Aoki, Michio Ono
  • Patent number: 4801997
    Abstract: Lead frame for mounting a semiconductor chip and improving the packing density of devices such as a plastic chip carrier type IC is disclosed. A portion of inner leads, located parallel to the chip stage and the edge of a molded case is made as thin as possible and held by inner lead supporting bars to tie bars until the molding process is finished. After molding process is finished, these bars supporting the leads and stage are cut away. Packing density is improved an amount ranging from 20% to 30%.
    Type: Grant
    Filed: April 19, 1988
    Date of Patent: January 31, 1989
    Assignee: Fujitsu Limited
    Inventors: Michio Ono, Akihiro Kubota, Tsuyoshi Aoki, Osamu Inoue, Rikio Sugiura
  • Patent number: 4724280
    Abstract: PLCC (Plastic Leaded Chip Carrier) for a LSI having protuberances on the bottom along its lateral side, is provided with interconnectors between leg portions of adjacent protuberances. Each interconnector is a swelling from the bottom surface of the main body of PLCC to fill the gap, i.e. a channel, between the protuberances. The height of the filling, namely the height of the interconnector, is lower than that of prior art protuberance to leave some space. This space, a channel, serves as a duct for solvent to flow therein smoothly to and from the narrow gap between the soldered lead and the top of the protuberance and is located adjoining this narrow gap. Therefore, the undesirably remaining flux in this narrow gap is perfectly removed by this smooth flow of the solvent. The leg portion of the protuberance is strengthened by the interconnector so that the occurrence of a crack of the protuberance when the moled PLCC is ejected from the molding cavities is considerably reduced.
    Type: Grant
    Filed: August 7, 1986
    Date of Patent: February 9, 1988
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Tsuyoshi Aoki, Michio Ono, Rikio Sugiura
  • Patent number: 4698660
    Abstract: A resin-molded semiconductor package device includes a plurality of grooves which are spaced a predetermined distance from each other in the edge portions defined by the main surface and the side surfaces of the main body of a resin-molded package, which grooves correspond to a plurality of external leads. The external leads are folded, the tips of the external leads are positioned in the grooves, and the middle portions of the external leads are located above the main surface of the package so that a predetermined standoff distance is maintained between the middle portions of the external leads and the package.
    Type: Grant
    Filed: February 12, 1986
    Date of Patent: October 6, 1987
    Assignee: Fujitsu Limited
    Inventors: Akihiro Kubota, Tsuyoshi Aoki, Michio Ono, Rikio Sugiura
  • Patent number: 4575748
    Abstract: A semiconductor device having a base which receives therein a semiconductor chip and a plurality of lead terminals having inner ends which are connected to the semiconductor chip by connecting wires. The lead terminals are, at their outer ends, spaced from one another at a constant pitch, and are bent toward the respective outermost lead terminals between the inner ends and the outer ends and outside the base.
    Type: Grant
    Filed: December 23, 1983
    Date of Patent: March 11, 1986
    Assignee: Fujitsu Limited
    Inventors: Kazuo Terui, Rikio Sugiura, Takehisa Sugawara
  • Patent number: RE35109
    Abstract: In a plastic molded semiconductor device in which inner leads overlap a semiconductor chip in a molded plastic body, the width of the chip may be close to the width of the plastic body without a decrease in the high resistance of the inner leads to the pull out thereof from the plastic body, and the layout of the inner leads may be unrestricted since the inner leads may occupy the region above the chip.
    Type: Grant
    Filed: January 7, 1993
    Date of Patent: December 5, 1995
    Assignee: Fujitsu Limited
    Inventors: Akihiro Kubota, Rikio Sugiura, Tsuyoshi Aoki, Michio Ono