Patents by Inventor Rikio Takase

Rikio Takase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of defining shape and position of dummy active region by processing data using a patterning apparatus
    Patent number: 8683406
    Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: March 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Mitsuaki Igeta, Masahiro Sueda, Rikio Takase, Akihiro Usujima
  • PATTERNING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20120297353
    Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 22, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Mitsuaki IGETA, Masahiro SUEDA, Rikio TAKASE, Akihiro USUJIMA
  • Fuse element reading circuit
    Patent number: 8072831
    Abstract: A fuse element reading circuit including a first fuse element having a resistance which differs in accordance with whether the first fuse element is in a blown state or an unblown state, a reference voltage output circuit unit that outputs a reference voltage that differs in accordance with a normal mode or a test mode, and a voltage comparison circuit unit that compares a read voltage corresponding to the resistance of the first fuse element with the reference voltage output from the reference voltage output circuit unit.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: December 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Rikio Takase, Masahiro Sueda
  • FUSE ELEMENT READING CIRCUIT
    Publication number: 20100014374
    Abstract: A fuse element reading circuit including a first fuse element having a resistance which differs in accordance with whether the first fuse element is in a blown state or an unblown state, a reference voltage output circuit unit that outputs a reference voltage that differs in accordance with a normal mode or a test mode, and a voltage comparison circuit unit that compares a read voltage corresponding to the resistance of the first fuse element with the reference voltage output from the reference voltage output circuit unit.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 21, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Rikio TAKASE, Masahiro Sueda
  • PATTERNING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20090315139
    Abstract: A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
    Type: Application
    Filed: March 19, 2009
    Publication date: December 24, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Mitsuaki IGETA, Masahiro SUEDA, Rikio TAKASE, Akihiro USUJIMA