Patents by Inventor Riko Radojcic

Riko Radojcic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thermal and stress gradient based RC extraction, timing and power analysis
    Patent number: 8797054
    Abstract: Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: August 5, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Hongmei Liao, Riko Radojcic
  • METHOD AND APPARATUS FOR CHARACTERIZING THERMAL MARGINALITY IN AN INTEGRATED CIRCUIT
    Publication number: 20130285687
    Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 31, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Tapan J. Chakraborty, Rajamani Sethuram, Riko Radojcic
  • THERMAL AND STRESS GRADIENT BASED RC EXTRACTION, TIMING AND POWER ANALYSIS
    Publication number: 20130033277
    Abstract: Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 7, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Hongmei Liao, Riko Radojcic