Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.

Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.

Abstract: Implementations of fault detection circuits may include a first current transformer coupled to a second current transformer, a positive feedback circuit including the first current transformer, the second current transformer, a first switch, and one of a comparator, an amplifier, and an inverter. The circuit may also include a plurality of logic gates that may be coupled with the positive feedback circuit. The positive feedback circuit may be configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates. The plurality of logic gates may be configured to analyze the fault signal and open the first switch. The plurality of logic gates may be further configured to identify whether the fault signal represents one of a true fault or a noise fault by analyzing the output of the positive feedback circuit after the first switch has been opened.

Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.

Abstract: Implementations of fault detection circuits may include a first current transformer coupled to a second current transformer, a positive feedback circuit including the first current transformer, the second current transformer, a first switch, and one of a comparator, an amplifier, and an inverter. The circuit may also include a plurality of logic gates that may be coupled with the positive feedback circuit. The positive feedback circuit may be configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates. The plurality of logic gates may be configured to analyze the fault signal and open the first switch. The plurality of logic gates may be further configured to identify whether the fault signal represents one of a true fault or a noise fault by analyzing the output of the positive feedback circuit after the first switch has been opened.

Abstract: Implementations of fault detection circuits may include a first current transformer coupled to a second current transformer, a positive feedback circuit including the first current transformer, the second current transformer, a first switch, and one of a comparator, an amplifier, and an inverter. The circuit may also include a plurality of logic gates that may be coupled with the positive feedback circuit. The positive feedback circuit may be configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates. The plurality of logic gates may be configured to analyze the fault signal and open the first switch. The plurality of logic gates may be further configured to identify whether the fault signal represents one of a true fault or a noise fault by analyzing the output of the positive feedback circuit after the first switch has been opened.

Abstract: Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.

Abstract: Implementations of fault detection circuits may include a first current transformer coupled to a second current transformer, a positive feedback circuit including the first current transformer, the second current transformer, a first switch, and one of a comparator, an amplifier, and an inverter. The circuit may also include a plurality of logic gates that may be coupled with the positive feedback circuit. The positive feedback circuit may be configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates. The plurality of logic gates may be configured to analyze the fault signal and open the first switch. The plurality of logic gates may be further configured to identify whether the fault signal represents one of a true fault or a noise fault by analyzing the output of the positive feedback circuit after the first switch has been opened.