Abstract: Display panels and display devices are provided. The display panel includes a functional module area and a plurality of first signal wirings arranged along a first direction. The display panel includes a first area and a second area, and along the first direction, the functional module area is disposed between the first area and the second area. The plurality of first signal wirings include a plurality of first cross-lines and a plurality of first sub-signal wirings along a second direction, the plurality of first sub-signal wirings are disposed in a display area, the plurality of first cross-lines are connected to the plurality of first sub-signal wirings, and the second direction intersects the first direction. The first area includes M first cross-lines of the plurality of first cross-lines, the second area includes N first cross-lines of the plurality of first cross-lines, and M is greater than N.

Abstract: Provided are a display panel and display device. The display panel includes: a sensor setting area and a first display area around the sensor setting area, where the sensor setting area includes at least one first area.

Abstract: Provided are a display panel and display device. The display panel includes: a sensor setting area and a first display area around the sensor setting area, where the sensor setting area includes at least one first area.

Abstract: Disclosed are a display panel and display device. The display panel includes: a sensor setting area and a display area around the sensor setting area, where the sensor setting area includes at least one photosensitive element setting area and each of the at least one photosensitive element setting area is the same.

Abstract: Display panels and display devices are provided. The display panel includes a functional module area and a plurality of first signal wirings arranged along a first direction. The display panel includes a first area and a second area, and along the first direction, the functional module area is disposed between the first area and the second area. The plurality of first signal wirings include a plurality of first cross-lines and a plurality of first sub-signal wirings along a second direction, the plurality of first sub-signal wirings are disposed in a display area, the plurality of first cross-lines are connected to the plurality of first sub-signal wirings, and the second direction intersects the first direction. The first area includes M first cross-lines of the plurality of first cross-lines, the second area includes N first cross-lines of the plurality of first cross-lines, and M is greater than N.

Abstract: Display panels and display devices are provided. The display panel includes a non-display area, a display area surrounding the non-display area, and a plurality of first signal wirings arranged along a first direction. The non-display area includes a first non-display area between adjacent through-holes of the at least two through-holes, a second non-display area located between the at least two through-holes and the display area, and at least two through-holes arranged along the first direction. The plurality of first signal wirings includes a plurality of first sub-signal wirings and a plurality of first cross-lines. Each end of the first cross-line is connected to one first sub-signal wiring; a number of first cross-lines of the plurality of first cross-lines in the first non-display area is M; a number of first cross-lines of the plurality of first cross-lines in the second non-display area is N; and M is greater than N.

Abstract: Display panels and display devices are provided. The display panel includes a non-display area, a display area surrounding the non-display area, and a plurality of first signal wirings arranged along a first direction. The non-display area includes a first non-display area between adjacent through-holes of the at least two through-holes, a second non-display area located between the at least two through-holes and the display area, and at least two through-holes arranged along the first direction. The plurality of first signal wirings includes a plurality of first sub-signal wirings and a plurality of first cross-lines. Each end of the first cross-line is connected to one first sub-signal wiring; a number of first cross-lines of the plurality of first cross-lines in the first non-display area is M; a number of first cross-lines of the plurality of first cross-lines in the second non-display area is N; and M is greater than N.

Abstract: Disclosed are a display panel and display device. The display panel includes: a sensor setting area and a display area around the sensor setting area, where the sensor setting area includes at least one photosensitive element setting area and each of the at least one photosensitive element setting area is the same.

Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes a display region and a non-display region surrounding the display region. The array substrate also includes a plurality of gate lines. The plurality of gate lines include a plurality of regular gate lines and at least one irregular gate line. The plurality of regular gate lines are disposed in the display region and extended along a first direction. The at least one irregular gate line includes at least one first trace portion and a second trace portion electrically connected to each other. The at least one first trace portion has a same line width as a regular gate line of the plurality of regular gate lines, and the second trace portion has a line width smaller than the at least one first trace portion.

Abstract: A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register.

Abstract: A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register.

Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes a display region and a non-display region surrounding the display region. The array substrate also includes a plurality of gate lines. The plurality of gate lines include a plurality of regular gate lines and at least one irregular gate line. The plurality of regular gate lines are disposed in the display region and extended along a first direction. The at least one irregular gate line includes at least one first trace portion and a second trace portion electrically connected to each other. The at least one first trace portion has a same line width as a regular gate line of the plurality of regular gate lines, and the second trace portion has a line width smaller than the at least one first trace portion.