Patents by Inventor Rimu Kaushal

Rimu Kaushal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9829962
    Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.
    Type: Grant
    Filed: December 18, 2016
    Date of Patent: November 28, 2017
    Assignee: NetSpeed Systems, Inc.
    Inventors: Rimu Kaushal, Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar
  • Patent number: 9785732
    Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 10, 2017
    Assignee: NetSpeed Systems, Inc.
    Inventors: Vishnu Mohan Pusuluri, Santhosh Patchamatla, Rimu Kaushal, Anup Gangwar, Sailesh Kumar
  • Publication number: 20170228481
    Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.
    Type: Application
    Filed: June 12, 2015
    Publication date: August 10, 2017
    Inventors: Vishnu Mohan PUSULURI, Santhosh PATCHAMATLA, Rimu KAUSHAL, Anup GANGWAR, Sailesh KUMAR
  • Publication number: 20170097672
    Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.
    Type: Application
    Filed: December 18, 2016
    Publication date: April 6, 2017
    Inventors: Rimu Kaushal, Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar
  • Publication number: 20170060212
    Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.
    Type: Application
    Filed: February 12, 2015
    Publication date: March 2, 2017
    Inventors: Rimu Kaushal, Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar
  • Patent number: 9568970
    Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: February 14, 2017
    Assignee: Netspeed Systems, Inc.
    Inventors: Rimu Kaushal, Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar