Abstract: A common problem in the manufacture of MOS ROM devices is the "antenna effect", whereby charges accumulate on long conductors (especially gate poly) during certain processing steps, particularly plasma processing. These charges can cause gate voltage sufficient to punch-through or break down thin gate oxide regions. By adding a "load" transistor to each length of conductor (e.g., by bank or row), and adjusting the size of the load transistor to cause total capacitance on the conductor to reach a minimum value, the antenna effect is minimized and process yield is improved. The size of the load transistor is determined based upon the amount of program-dependent capacitive load placed on each conductor (i.e., the number of transistor gates connected to the conductor). One aspect of the invention provides for omitting the load transistor if there is no load on a conductor (i.e.