Patents by Inventor Rina Panigrahy

Rina Panigrahy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050226263
    Abstract: Weighted random scheduling is preformed, which may be particularly applicable to packet switching systems. For each particular input of multiple switch inputs, a request to send a packet to one of the outputs of the switch is generated by weighted randomly selecting one of the outputs to which the particular input has one or more packets to send. One of the requests is granted for each different one of the outputs for which one or more requests were generated. Packets are sent between the inputs and the output corresponding to the granted requests. The weighted random selection is typically weighted based on the number of packets or bytes to send to each of the outputs by a corresponding input of the inputs, the last times packets were sent from a corresponding input of the inputs to each of the outputs, and/classes of service associated with packets to send to each of the outputs by a corresponding input of the inputs.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 13, 2005
    Applicant: Cisco Technology, Inc., A California Corporation
    Inventors: Rina Panigrahy, Awais Nemat
  • Patent number: 6725326
    Abstract: Techniques for efficient memory management that enable rapid longest prefix match lookups in memory. In general, the present invention is efficacious wherever maintenance of a good distribution of holes in a sorted list is required. This technique relies on a proactive hole management methodology to preserve a good distribution of holes in each memory region in such a way that one does not have to search for holes in order to insert or store a new entry into the list. In particular, all holes in a given region are kept in one or more contiguous sub-region. Keeping the holes contiguous requires a hole move every time there is a delete operation. The amortized cost of these operations is justified by the resulting simplification in later insert (store) and delete operations. For example, during an insert the new entry is placed at the end of the contiguous sub-region of used entries in the region.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: April 20, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Abhijit Patra, Rina Panigrahy, Samar Sharma
  • Patent number: 6717946
    Abstract: Methods and apparatus are disclosed for maintaining one or more ranges and identifying whether a value matches one of the ranges and optionally which range is matched. One implementation includes a range programming engine for generating one or more mapped subtrie values identifying each range, each of the mapped subtrie values identifying a different subset of the range. An associative memory stores the mapped subtrie ranges. A mapping engine receives a particular value and generates a lookup word including a mapped representation of the particular value. The associative memory performs a lookup operation to identify whether or not the particular value is within one of the ranges. In this manner, only a small number of associative memory entries are required to identify whether a mapped particular value falls within the range. The particular range matched can be identified such as by a read operation in an adjunct memory based on the address of the matching entry.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: April 6, 2004
    Assignee: Cisco Technology Inc.
    Inventors: Yoichi Hariguchi, Rina Panigrahy, Samar Sharma, Ashwath Nagaraj
  • Patent number: 6553420
    Abstract: The invention relates to a method and apparatus for requesting data from one of a plurality of servers. A virtual network of nodes is generated in response to a data request. A first node on the virtual network of nodes is chosen randomly, and a path generated from the first node to the root on the virtual network. At least one node on the path is mapped to a respective one of the plurality of servers and data is requested from a server. The node may be mapped to the server using the method and apparatus for distributing a request to one of a plurality of resources of the present invention.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: April 22, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: David Karger, Eric Lehman, F. Thomson Leighton, Matthew Levine, Daniel Lewin, Rina Panigrahy
  • Patent number: 6516383
    Abstract: Techniques for the efficient location of free entries for use in performing insert operations in a binary or ternary content addressable memory. As used in data communications and packet routing, such memories often rely on an organization that maintains entries of the same “length” within defined regions. The present invention keeps the free entries (holes) compacted into a contiguous subregion within each region, without requiring hole movement during deletes. These positive effects are accomplished by initially pre-filling the entire memory with a set of hole codes that each uniquely identify the holes in each region. A conventional memory write is then performed to load routing data into the memory. Typically, such routing information will not fill the entire memory, leaving unused entries (containing the region appropriate hole code) in each region. As entries need to be deleted, they are simply replaced by writing in the region-unique hole code.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: February 4, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Abhijit Patra, Rina Panigrahy, Samar Sharma