Abstract: The present invention provides compensation for circuits. In one embodiment, a compensation circuit has a first terminal coupled to an output terminal of the circuit and a second terminal coupled to feed back the output voltage to an internal node. A damping circuit may also be coupled to the output terminal. The damping circuit adds a pole and a zero to the transfer function of the circuit. In one embodiment, the damping circuit modifies the effect of the output impedance of a load on the transfer function to increase the phase margin of the circuit such that the circuit remains stable over an increased range of output capacitor values.

Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor.

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.

Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.

Abstract: A switched input circuit structure of the type which includes an input terminal receiving an input voltage and an output terminal connected to an input capacitor. An operational amplifier is included having a non-inverting terminal connected to a ground reference terminal, an inverting input terminal, and an output terminal feedback connected to the inverting input terminal and held in a virtual ground condition by a parallel of first and second charge paths which are connected between the input terminal of the switched input circuit structure and the inverting input terminal of the operational amplifier and connected to the supply voltage reference and the ground reference, respectively.

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Abstract: The invention relates to an elementary biquadratic cell for programmable time-continuous analog filters. The biquadratic cell is coupled between a first voltage reference and a second voltage reference and has at least one pair of input terminals and first and second pairs of output terminals. The cell includes a pair of half-cells, which half-cells are structurally identical with each other. Each half-cell comprises at least a first transistor coupled between the first and the second voltage reference and having a base terminal connected to a respective one of the input terminals. Each half-cell further comprises second and third transistors coupled between the first and second voltage references. The second transistor has a base terminal connected to the first output terminal of the first pair of output terminals and a collector terminal connected to the first output terminal of the second pair of output terminals.

Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.

Abstract: A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.

Abstract: In a switched operational amplifier including a differential input stage and at least a second output stage, the compensation capacitor commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with a switching circuit. The switching circuit is controlled by the same control phase that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage and an amplifier output stage connected serially together to receive an input signal on at least one input terminal of the amplifier and generate an amplified signal on an output terminal of the amplifier. Provided between the input and output stages is an intermediate node which is connected to a compensation block to receive a frequency-variable compensation signal therefrom. The compensation block is coupled with its input to the input terminal of the amplifier. The compensation block is connected to receive at least the feedback signal. Preferably, the compensation signal is variable as a function of a gain value which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value.

Abstract: In switch-capacitor systems for extremely low supply voltage, employing a fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal is made possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.

Abstract: An interface circuit is disposed between a generator of control signals and a plurality of electronic switches in order to produce boosted voltage signals corresponding to the control signals for activating the electronic switches. To avoid the use of a capacitor with a high capacitance and thus to reduce an area of the integrated circuit, the interface circuit includes a generator of activation signals and a plurality of voltage multipliers each having an input connected to an output of the control signal generator, an output connected to at least one terminal for activating an electronic switch and two control terminals connected to an activation signal generator. Each voltage multiplier includes MOS transistors operatively coupled in series between the input and the output. The MOS transistors operate in response to the activation signals to produce a boosted voltage on the capacitor.

Abstract: A digital-to-analog converter includes a potentiometric string suitable for realizing a relatively high number of bits that significantly reduces the silicon area requirement and simplifies mismatch compensation. The structure includes a first resistance string to realize a first DAC to convert a first number of most significative bits, and a second potentiometric string functionally connected in cascade to the first, but realized with MOS transistors. The structure of the invention allows the coupling of the two DACs in cascade by exploiting the MOS transistors that form the second potentiometric string, that is, the second DAC, thus avoiding the use of operational switches or amplifiers which may provide error sources. Moreover, the structure of the invention lends itself to the implementation of efficient compensation circuits for integral and differential linearity errors.

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage and an amplifier output stage connected serially together to receive an input signal on at least one input terminal of the amplifier and generate an amplified signal on an output terminal of the amplifier. Provided between the input and output stages is an intermediate node which is connected to a compensation block to receive a frequency-variable compensation signal therefrom. The compensation block is coupled with its input to the input terminal of the amplifier The compensation block is connected to receive at least the feedback signal. Preferably, the compensation signal is variable as a function of a gain value which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value.

Abstract: An integrated operational amplifier with adjustable frequency compensation having a transconductance input stage and an amplifier output stage connected serially together between an input terminal and an output terminal of the operational amplifier. For the purpose of frequency compensation, moreover, a compensation block is connected across the input and the output of the output stage. The compensation block uses a plurality of charge storage elements connected in parallel together and in series with switch block which selects a sub-plurality of said charge storage elements in response to an external signal of the amplifier. The compensation block thereby provides an overall effective capacitance for frequency compensation.

Abstract: A high-pass filter includes at least one circuit unit constituted by a first branch and a second branch both connected to an input of the filter on one side and, on the other side, to an adder the output of which is the output of the filter. The first branch includes means for transferring an input signal substantially without modifying its frequency content, and the second branch comprises a low-pass filter. The circuit elements are chosen such that the components of the input signal with frequencies below the cut-off frequency of the low-pass filter are substantially cancelled out at the output of the adder. The filter is suitable for being produced within a particularly small area in an integrated circuit.

Abstract: A switching circuit utilizing MOS transistors without body effect having a first transistor inserted with source and drain terminals between two connection terminals, and a second and third transistors inserted in series by means of their respective source and drain terminals between the first transistor and a ground. The gate terminal of the second transistor is connected to the gate terminal of the first transistor to which is applied a command signal. Upon switching a signal is applied in phase opposition to the command signal to the gate terminal of the third transistor. The substrates of the first and the second transistors are connected to a connection node between the second and third transistors. The substrate of the third transistor is connected to ground.