Patents by Inventor Rinat Rappoport

Rinat Rappoport has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200241877
    Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
    Type: Application
    Filed: July 1, 2017
    Publication date: July 30, 2020
    Applicant: Intel Corporation
    Inventors: Menachem ADELMAN, Robert VALENTINE, Zeev SPERBER, Mark J. CHARNEY, Bret L. TOLL, Rinat RAPPOPORT, Jesus CORBAL, Dan BAUM, Alexander F. HEINECKE, Elmoustapha OULD-AHMED-VALL, Yuri GEBIL, Raanan SADE
  • Publication number: 20200233666
    Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory.
    Type: Application
    Filed: July 1, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Robert VALENTINE, Menachem ADELMAN, Elmoustapha OULD-AHMED-VALL, Bret L. TOLL, Milind B. GIRKAR, Zeev SPERBER, Mark J. CHARNEY, Rinat RAPPOPORT, Jesus CORBAL, Stanislav SHWARTSMAN, Igor YANOVER, Alexander F. HEINECKE, Barukh ZIV, Dan BAUM, Yuri GEBIL
  • Publication number: 20200233667
    Abstract: Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.
    Type: Application
    Filed: July 1, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Robert VALENTINE, Zeev SPERBER, Mark J. CHARNEY, Bret L. TOLL, Rinat RAPPOPORT, Stanislav SHWARTSMAN, Dan BAUM, Igor YANOVER, Elmoustapha OULD-AHMED-VALL, Menachem ADELMAN, Jesus CORBAL, Yuri GEBIL, Simon RUBANOVICH
  • Publication number: 20200110608
    Abstract: Embodiments of an apparatus comprising a decoder to decode an instruction having fields for an opcode and a destination operand and execution circuitry to execute the decoded instruction to perform a save of processor state components to an area located at a destination memory address specified by the destination operand, wherein a size of the area is defined by at least one indication of an execution of an instruction operating on a specified group of processor states are described.
    Type: Application
    Filed: July 1, 2017
    Publication date: April 9, 2020
    Applicant: Intel Corporation
    Inventors: Robert VALENTINE, Mark J. CHARNEY, Rinat RAPPOPORT, Vivekananthan SANJEEPAN
  • Patent number: 10592421
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A. Goldsmith, Barry E. Huntley, Anton Ivanov, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott D. Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, William C. Wood
  • Publication number: 20200065352
    Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
    Type: Application
    Filed: July 1, 2017
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Robert VALENTINE, Mark J. CHARNEY, Elmoustapha OULD-AHMED-VALL, Dan BAUM, Zeev SPERBER, Jesus CORBAL, Bret L. TOLL, Raanan SADE, Igor YANOVER, Yuri GEBIL, Rinat RAPPOPORT, Stanislav SHWARTSMAN, Menachem ADELMAN, Simon RUBANOVICH
  • Patent number: 10503517
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Publication number: 20190042448
    Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.
    Type: Application
    Filed: December 22, 2017
    Publication date: February 7, 2019
    Inventors: Raanan SADE, Jason BRANDT, Mark J. CHARNEY, Joseph NUZMAN, Leena PUTHIYEDATH, Rinat RAPPOPORT, Vivekananthan SANJEEPAN, Robert VALENTINE
  • Publication number: 20180060078
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Application
    Filed: August 8, 2017
    Publication date: March 1, 2018
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V, Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 9727345
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russell J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 9594807
    Abstract: Embodiments of techniques, apparatuses and systems associated with emotion information processing are disclosed. In some embodiments, a computing system may receive an image of a person and identify an emotional state of the person, based at least in part on the image. The computing system may cause storage of the emotional state of the person in combination with other data to enable subsequent response to an emotion-related query provided to the computing system. The emotion-related query may include an emotion-related criteria and a non-emotion-related criteria and the response may be based at least in part on the emotional state in combination with at least some of the other data. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Rinat Rappoport, Raanan Yehezkel, Roman Fishtein, Sergei Goffman, Guy Jacob, Oren Gershon, Andrey Sloutsman, Ido Lapidot, Ofer Givoli
  • Publication number: 20160371191
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: CARLOS V. ROZAS, ILYA ALEXANDROVICH, ITTAI ANATI, ALEX BERENZON, MICHAEL A. GOLDSMITH, BARRY E. HUNTLEY, ANTON IVANOV, SIMON P. JOHNSON, REBEKAH M. LESLIE-HURD, FRANCIS X. MCKEEN, GILBERT NEIGER, RINAT RAPPOPORT, SCOTT D. RODGERS, UDAY R. SAVAGAONKAR, VINCENT R. SCARLATA, VEDVYAS SHANBHOGUE, WESLEY H. SMITH, WILLIAM C. WOOD
  • Patent number: 9430384
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: March 31, 2013
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Carlos V Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A Goldsmith, Barry E Huntley, Anton Ivanov, Simon P Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott Dion Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H Smith, William Colin Wood
  • Publication number: 20150193507
    Abstract: Embodiments of techniques, apparatuses and systems associated with emotion information processing are disclosed. In some embodiments, a computing system may receive an image of a person and identify an emotional state of the person, based at least in part on the image. The computing system may cause storage of the emotional state of the person in combination with other data to enable subsequent response to an emotion-related query provided to the computing system. The emotion-related query may include an emotion-related criteria and a non-emotion-related criteria and the response may be based at least in part on the emotional state in combination with at least some of the other data. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 6, 2013
    Publication date: July 9, 2015
    Inventors: Rinat Rappoport, Raanan Yehezkel, Roman Fishtein, Sergei Goffman, Guy Jacob, Oren Gershon, Andrey Sloutsman, Ido Lapidot, Ofer Givoli
  • Publication number: 20140297962
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Application
    Filed: March 31, 2013
    Publication date: October 2, 2014
    Inventors: CARLOS V ROZAS, ILYA ALEXANDROVICH, ITTAI ANATI, ALEX BERENZON, MICHAEL A GOLDSMITH, BARRY E HUNTLEY, ANTON IVANOV, SIMON P JOHNSON, REBEKAH M. LESLIE-HURD, FRANCIS X. MCKEEN, GILBERT NEIGER, RINAT RAPPOPORT, SCOTT DION RODGERS, UDAY R. SAVAGAONKAR, VINCENT R. SCARLATA, VEDVYAS SHANBHOGUE, WESLEY H SMITH, WILLIAM COLIN WOOD
  • Publication number: 20140281457
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Application
    Filed: March 29, 2013
    Publication date: September 18, 2014
    Inventors: Elierzer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 8249853
    Abstract: An embodiment of the present invention is a technique to process an input/output (I/O) transaction. An emulated device driver in a guest partition interacts with a virtual machine (VM) manager in processing an input/output (I/O) transaction on behalf of an application via an operating system (OS). The I/O transaction is between the application and a device. A device emulator in a service partition communicatively coupled to the emulated device driver interacts with the VM manager in processing the I/O transaction on behalf of a device specific driver via the OS. The device specific driver interfaces to the device.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Jeff Jackson, Rinat Rappoport, Sergei Gofman, Michael D. Kinney
  • Publication number: 20110016290
    Abstract: In one embodiment, a method includes receiving control of a first processor transitioned from a virtual machine due to a privileged event pertaining to a translation-lookaside buffer, and determining which entries in a guest translation data structure were modified by the virtual machine. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor and attributes associated with entries in the shadow translation data structure. The metadata includes an active entry list identifying mappings that map pages used by a guest operating system in forming the guest translation data structure.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Inventors: Arie Chobotaro, Rinat Rappoport, Andrew V. Anderson, Baruch Chaikin
  • Patent number: 7865712
    Abstract: Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether an encrypted version of a closed operating system is authentic may be determined. The encrypted version of the closed operating system may be decrypted with a key retrieved from a processor register to provide the closed operating system, based at least in part on a determination that the encrypted version of the closed operating system is authentic. Then, whether the closed operating system is authentic may be determined and a virtual machine may be created so that the closed operating system may be launched in the virtual machine, if the closed operating system is authentic.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: January 4, 2011
    Assignee: Intel Corporation
    Inventors: Konstantin Levit-Gurevich, Rinat Rappoport
  • Publication number: 20100023739
    Abstract: Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether an encrypted version of a closed operating system is authentic may be determined. The encrypted version of the closed operating system may be decrypted with a key retrieved from a processor register to provide the closed operating system, based at least in part on a determination that the encrypted version of the closed operating system is authentic. Then, whether the closed operating system is authentic may be determined and a virtual machine may be created so that the closed operating system may be launched in the virtual machine, if the closed operating system is authentic.
    Type: Application
    Filed: December 26, 2007
    Publication date: January 28, 2010
    Inventors: Konstantin Levit-Gurevich, Rinat Rappoport