Abstract: Embodiments disclosed herein include an apparatus for bump translation. In an embodiment, the apparatus includes a substrate with a first bump field with a first height and a first depth on the substrate, where the first depth is orthogonal to the first height, and where the first bump field further comprises a first pitch in a direction of the first height. In an embodiment, the apparatus includes a second bump field with a second height and a second depth on the substrate, where the second depth is orthogonal to the second height, and where the second bump field comprises a second pitch in a direction of the second height, where the second pitch is smaller than the first pitch. Embodiments include a third bump field with a third height and the second depth, where a sum of the second height and the third height is equal to the first height.

Abstract: A transceiver may include a transmitter device, a receiver device, a secondary receiver device, and switching elements. The transmitter device may provide a transmit control signal on first and second channels. The receiver device may receive a receive control signal on the first and second channels. The secondary receiver device may monitor occupation of the first and second channels without decoding at least a portion of control signals concurrent with the receiver device receiving the receive control signal. The switching elements may control when the transmitter device provides the transmit control signal to one of and is electrically isolated from first and second antennas, the receiver device receives the receive control signal from one of and is electrically isolated from the first and second antennas, and the secondary receiver device monitors occupation of one of the first and second channels and is electrically isolated from the first and second antennas.

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

Abstract: A transceiver may include a transmitter device, a receiver device, a secondary receiver device, and switching elements. The transmitter device may provide a transmit control signal on first and second channels. The receiver device may receive a receive control signal on the first and second channels. The secondary receiver device may monitor occupation of the first and second channels without decoding at least a portion of control signals concurrent with the receiver device receiving the receive control signal. The switching elements may control when the transmitter device provides the transmit control signal to one of and is electrically isolated from first and second antennas, the receiver device receives the receive control signal from one of and is electrically isolated from the first and second antennas, and the secondary receiver device monitors occupation of one of the first and second channels and is electrically isolated from the first and second antennas.

Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.

Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract: Described is an apparatus comprising: an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load; an amplifier to control current strength of the output stage according to the output supply and a reference voltage; and a hysteresis unit to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply. Described is another apparatus which comprises: a plurality of charge pumps to adjust current strength of the output stage; and a logic unit to monitor the output supply and operable to control the plurality of charge pumps according to a voltage level of the output supply and one or more reference voltages.

Abstract: An output stage has an input supply node to receive an input power supply and an output node to provide an output supply to a load. An amplifier is used to control current strength of the output stage according to the output supply and a reference voltage. A hysteresis unit is used to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply. In one embodiment, a plurality of charge pumps are used to adjust current strength of the output stage. A logic unit is used to monitor the output supply and operable to control the plurality of charge pumps according to a voltage level of the output supply and one or more reference voltages.