Abstract: One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width and a second threshold voltage that is less than the first threshold voltage. Other circuits and methods are also disclosed.

Abstract: A semiconductor device comprising a first transistor device and second transistor device both on a semiconductor substrate. The first transistor device has a first n-channel and a first p-channel and the second transistor device has a second n-channel and a second p-channel. Each of the p-channels and the n-channels have a long lateral axis that is aligned with a orientation plane of a silicon layer of the semiconductor substrate. The second p-channel and the first and second n-channels include the silicon layer configured as strained silicon. The first p-channel includes the silicon layer configured as relaxed silicon. Each of the n-channels contact gate structures that impart a tensile stress in the n-channels.

Abstract: One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.

Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.

Abstract: Embodiments provide a method of fabricating a plurality of planar nanowires surround gate semiconductor device. The planar nanowires can be formed between a source and a drain over an insulating layer of a semiconductor substrate. A gate stack can be grown or deposited all-around the planar nanowires. The gate stack can then be etched and patterned. During this process, the planar nanowires are severed between the gate and the source, and between the gate and the drain, leaving portions of the gate-all-around planar nanowires remain between the source and the drain and serve as the active region of the channel. The remaining gate-all-around planar nanowires can be epitaxially regrown to reconnect to the source and the drain.

Abstract: A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, a method of manufacture therefore, and an integrated circuit including the same. The metal oxide semiconductor (MOS) device (100), without limitation, may include a first accumulation mode transistor device (120, 160) located over or in a substrate (110), as well as a second enhancement mode transistor (140, 180) device located over or in the substrate (110).

Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device includes an oxide layer. The semiconductor device also includes a silicon layer disposed outwardly from the oxide layer and having at least one region comprising a dopant. The semiconductor device also includes a dielectric layer disposed outwardly from the silicon layer. The semiconductor device also includes a gate disposed outwardly from the dielectric layer. The semiconductor device also includes a blocking layer disposed between the oxide layer and the silicon layer. The blocking layer is operable to at least partially block a transfer of the dopant from the at least one region of the silicon layer to the oxide layer.

Abstract: A method and system for generating and managing a knowledgebase for use in identifying anomalies on a manufactured object, such as a semiconductor wafer, includes measures for adding, deleting, and organizing data from the knowledgebase.

Abstract: A system and method allow for associating a descriptive label with an anomaly on a manufactured object, such as a semiconductor wafer. The method includes placing the manufactured device on a moveable stage; capturing and preparing a digital-pixel-based representation of the image; symbolically decomposing the digital-pixel-based representation of the image to create a primitive-based representation of the image; analyzing the primitive-based representation of the image to detect and locate the anomaly; isolating primitives associated with the anomaly; comparing the isolated primitives associated with the anomaly with primitives in a knowledge base to locate a set of primitives in the knowledge base most like the isolated primitives associated with the anomaly; and assigning a label associated with the set of primitives in the knowledge base that was most similar to the isolated primitives associated with the anomaly.

Abstract: A method and system for generating and managing a knowledgebase for use in identifying anomalies on a manufactured object, such as a semiconductor wafer, includes measures for adding, deleting, and organizing data from the knowledgebase.

Abstract: A system and method for repairing a defect on a manufactured object, which may be a semiconductor wafer, uses a computer and a repair tool.

Abstract: A tornado detector comprising a sensor (30) for sensing the presence of sound having a frequency of about one hertz and for providing a sound sense signal in response thereto, a filter (50) to attenuate said sound sense signal wave components having frequencies greater than those which correspond to sound having a frequency of about one hertz, and an alarm (101) for generating an alarm signal in response to said filtered sound sense signal.

Abstract: One embodiment of the instant invention is a process chamber for heating a semiconductor wafer, the process chamber comprising: heating elements (elements 104 of FIG. 2a) for providing heating energy; means for holding (means 112 of FIG. 2a) the semiconductor wafer; and shutters situated between the heating elements and the means for holding the semiconductor wafer, the shutters (shutters 108 of FIGS. 2a and 2b and shutters of FIGS. 2c and 2d for blocking the heating energy from getting to the semiconductor wafer when the shutters are in a closed position and for directing the heating energy to the semiconductor wafer when in an open position.

Abstract: A method is provided for aligning a silicon wafer (20) in a fabrication tool (37) having a stage (22) involving the steps of producing a digital image of a portion of wafer (20) in a scope-of-view window (48), converting the digital image to image primitives, comparing the image primitives to grammar template primitives to locate a known intersection on wafer (20); and moving the stage (22) to align wafer (20). A method and apparatus are disclosed for determining the misregistration of two layers of a wafer (20) by converting targets (158, 160) to primitives and determining the relative displacement in symbolic space. The misregistration apparatus involves a camera (34), a video-to-digital converter (32), a computer (28), and a stage adjuster (24).

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

Abstract: A process for removing at least a portion of a film from a substrate, such as a wafer of silicon or other similar materials, the film on the substrate typically being an oxide film, maintaining the atmosphere embracing the substrate at near room temperature and at near normal atmospheric pressure, flowing dry inert diluent gas over the substrate, introducing a flow of reactive gas, preferably an anhydrous hydrogen halide gas, namely anhydrous hydrogen flouride gas, for typically 5 to 30 seconds over the substrate and film to cause the removal of portions of the film, flowing water vapor laden inert gas, preferably nitrogen, over the substrate and film from a time prior to commencing flow of the reactive gas until flow of the reactive gas is terminated. In the case of non-hygroscopic film on the substrate, the flow of water vapor continues during the flow of the reactive gas and is terminated shortly after the termination of the flow of reactive gas.