Abstract: Provided is a capacitive micromachined ultrasonic transducer (CMUT) including a substrate, a top electrode provided on the substrate to be spaced apart from the substrate, a supporter made of an insulating material and coupled between the substrate and an edge of the top electrode to support and fix the edge of the top electrode and to define a gap between the substrate and the edge of the top electrode, and a plurality of nanoposts having both ends coupled and fixed to the substrate and the top electrode in the gap, and being compressible and stretchable in a longitudinal direction to at least vertically move the top electrode when power is applied to the top electrode.

Abstract: Provided is a method for manufacturing a multilayer structure. The method for manufacturing the multilayer structure includes providing a substrate in a chamber, providing a target in the chamber, and allowing a target material to be incident into the substrate so as to form a material layer. The target includes magnesium oxide or beryllium oxide. An incident angle of the target material to the substrate is about 9.14° or less.

Abstract: Provided is a capacitive micromachined ultrasonic transducer (CMUT) including a substrate, a top electrode provided on the substrate to be spaced apart from the substrate, a supporter made of an insulating material and coupled between the substrate and an edge of the top electrode to support and fix the edge of the top electrode and to define a gap between the substrate and the edge of the top electrode, and a plurality of nanoposts having both ends coupled and fixed to the substrate and the top electrode in the gap, and being compressible and stretchable in a longitudinal direction to at least vertically move the top electrode when power is applied to the top electrode.

Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

Abstract: Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.

Abstract: Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.

Abstract: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without removing the mask layer, a second metal layer may be deposited. In one embodiment, the mask layer is a second metal layer. In other embodiments, the mask layer is a silicon layer. Subsequent fabrication steps include depositing another metal layer (e.g., another PMOS metal layer), depositing a cap, etching the cap to define gate stacks, and simultaneously etching the first and second gate region having a similar thickness with differing metal layers.