Patents by Inventor Rinus Tek Po Lee

Rinus Tek Po Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143254
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 13, 2021
    Inventors: Jiehui SHU, Rinus Tek Po LEE, Baofu ZHU
  • Patent number: 11004953
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Rinus Tek Po Lee, Hui Zang, Jiehui Shu, Hong Yu, Wei Hong
  • Patent number: 10896853
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 19, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Rinus Tek Po Lee, Wei Hong, Hui Zang, Hong Yu
  • Publication number: 20210013109
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Bharat V. KRISHNAN, Rinus Tek Po LEE, Jiehui SHU, Hyung Yoon CHOI
  • Publication number: 20200411664
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: RINUS TEK PO LEE, HUI ZANG, JIEHUI SHU, HONG YU, WEI HONG
  • Publication number: 20200343142
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: JIEHUI SHU, RINUS TEK PO LEE, WEI HONG, HUI ZANG, HONG YU
  • Publication number: 20200312775
    Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: RINUS TEK PO LEE, FUAD AL-AMOODY, ASLI SIRMAN, JOSEPH KYALO KASSIM, HUI ZANG, BHARAT V. KRISHNAN
  • Patent number: 10418365
    Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee
  • Patent number: 10211045
    Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rishikesh Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard, Jr., Rinus Tek Po Lee, Yiheng Xu
  • Patent number: 10204904
    Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Rinus Tek Po Lee
  • Publication number: 20190035791
    Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 31, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee
  • Patent number: 10134739
    Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee
  • Patent number: 10134876
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bharat V. Krishnan, Timothy J. McArdle, Rinus Tek Po Lee, Shishir K. Ray, Akshey Sehgal
  • Publication number: 20180331097
    Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.
    Type: Application
    Filed: May 10, 2017
    Publication date: November 15, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Rinus Tek Po Lee
  • Publication number: 20180286982
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Bharat V. KRISHNAN, Timothy J. MCARDLE, Rinus Tek Po LEE, Shishir K. Ray, Akshey SEHGAL
  • Publication number: 20150111372
    Abstract: Provided are methods for preparing a doped silicon material. The methods include contacting a surface of a silicon material with a dopant solution comprising a dopant-containing compound selected from a phosphorus-containing compound and an arsenic-containing compound, to form a layer of dopant material on the surface; and diffusing the dopant into the silicon material, thereby forming the doped silicon material, wherein the doped silicon material has a sheet resistance (Rs) of less than or equal to 2,000 ?/sq.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Applicant: SEMATECH, INC.
    Inventors: Robert TIECKELMANN, Wei-Yip LOH, Rinus Tek Po LEE
  • Patent number: 8829567
    Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 9, 2014
    Assignee: Sematech, Inc.
    Inventors: Rinus Tek Po Lee, Tae Woo Kim, Man Hoi Wong, Richard Hill
  • Publication number: 20140183597
    Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: SEMATECH, INC.
    Inventors: Rinus Tek Po LEE, Tae Woo KIM, Man Hoi WONG, Richard HILL
  • Patent number: 7015132
    Abstract: A method of constructing an electrical contact on an electronic component comprises first forming a protruding electrically conducting stud at a contact location by wire bonding a metal wire to a contact pad of the component. The stud is then contacted with solder, without using a mask, so that a solder bump is deposited on and adheres to the metal stud to form a composite solder contact which is able to form with a contact of another component a solder joint which has good electrical and mechanical properties and which may be reliable fabricated at high density by a low cost method. An electronic component provided with such solder contacts and an electronics component package including such a component are also disclosed.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: March 21, 2006
    Assignee: Agency for Science, Technology and Research
    Inventors: Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah
  • Publication number: 20020102765
    Abstract: A method of constructing an electrical contact on an electronic component comprises first forming a protruding electrically conducting stud at a contact location by wire bonding a metal wire to a contact pad of the component. The stud is then contacted with solder, without using a mask, so that a solder bump is deposited on and adheres to the metal stud to form a composite solder contact which is able to form with a contact of another component a solder joint which has good electrical and mechanical properties and which may be reliable fabricated at high density by a low cost method. An electronic component provided with such solder contacts and an electronics component package including such a component are also disclosed.
    Type: Application
    Filed: January 2, 2002
    Publication date: August 1, 2002
    Inventors: Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah