Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.

Abstract: A structure comprises a substrate and a first gate structure and a second gate structure in a dielectric layer over the substrate. The first and second gate structures having a width, the width of the first gate structure is shorter than the width of the second gate structure. The first gate structure comprises a first gate conductor layer and the second gate structure comprises a second gate conductor layer. The first gate conductor layer is made of a different metal from the second gate conductor layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages.

Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.

Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

Abstract: Provided are methods for preparing a doped silicon material. The methods include contacting a surface of a silicon material with a dopant solution comprising a dopant-containing compound selected from a phosphorus-containing compound and an arsenic-containing compound, to form a layer of dopant material on the surface; and diffusing the dopant into the silicon material, thereby forming the doped silicon material, wherein the doped silicon material has a sheet resistance (Rs) of less than or equal to 2,000 ?/sq.

Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.