Patents by Inventor Ripan Das
Ripan Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315143Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: June 5, 2023Publication date: October 5, 2023Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Patent number: 11726910Abstract: Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.Type: GrantFiled: March 12, 2020Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Ian M. Steiner, Andrew J. Herdrich, Wenhui Shu, Ripan Das, Dianjun Sun, Nikhil Gupta, Shruthi Venugopal
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Patent number: 11703906Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: GrantFiled: November 5, 2021Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Publication number: 20220129031Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: November 5, 2021Publication date: April 28, 2022Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Publication number: 20220100247Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 26, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Haake, Andrew Herdrich, Ripan Das
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Patent number: 11169560Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: GrantFiled: February 24, 2017Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris Macnamara, John J. Browne, Ripan Das
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Publication number: 20200210332Abstract: Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.Type: ApplicationFiled: March 12, 2020Publication date: July 2, 2020Inventors: Ian M. STEINER, Andrew J. HERDRICH, Wenhui SHU, Ripan DAS, Dianjun SUN, Nikhil GUPTA, Shruthi VENUGOPAL
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Publication number: 20190384348Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: February 24, 2017Publication date: December 19, 2019Inventors: Vasudevan SRINIVASAN, Krishnakanth V. SISTLA, Corey D. GOUGH, Ian M. STEINER, Nikhil GUPTA, Vivek GARG, Ankush VARMA, Sujal A. VORA, David P. LERNER, Joseph M. SULLIVAN, Nagasubramanian GURUMOORTHY, William J. BOWHILL, Venkatesh RAMAMURTHY, Chris MACNAMARA, John J. BROWNE, Ripan DAS
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Publication number: 20170185128Abstract: An electronic device may be provided that includes logic, at least a portion which is hardware, to receive a plurality of transition requests within a configurable moving time period and to block a clock signal to one or more of the plurality of cores based on the received transition requests.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Venkatesh Ramamurthy, Ripan Das
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Patent number: 9231434Abstract: A method and system for applying a multi-rate charge to a battery are included herein. The method includes detecting a plurality of predetermined electrical measurements and a plurality of predetermined charge currents. The method also includes detecting an electrical measurement of the battery. Additionally, the method includes selecting a charge current from the plurality of predetermined charge currents to be applied to the battery based on the electrical measurement of the battery and the plurality of predetermined electrical measurements. Furthermore, the method includes applying the charge current to the battery. The method also includes detecting a plurality of subsequent electrical measurements of the battery. In addition, the method includes applying a plurality of subsequent charge currents to the battery based on the plurality of subsequent electrical measurements of the battery and the plurality of predetermined charge currents.Type: GrantFiled: June 26, 2012Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Ripan Das, Nagasubramanian Gurumoorthy, Andy Keates
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Publication number: 20140184163Abstract: In one embodiment a method comprises receiving, in the controller, a user profile for usage of an electronic device, the electronic device at least partially powered by a battery and implementing, in the controller, a selected charge routine from a plurality of charge routines for the battery based at least in part on the user profile. Other embodiments may be described.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: RIPAN DAS, NAGASUBRAMANIAN GURUMOORTHY, ANDY KEATES
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Publication number: 20130342173Abstract: A method and system for applying a multi-rate charge to a battery are included herein. The method includes detecting a plurality of predetermined electrical measurements and a plurality of predetermined charge currents. The method also includes detecting an electrical measurement of the battery. Additionally, the method includes selecting a charge current from the plurality of predetermined charge currents to be applied to the battery based on the electrical measurement of the battery and the plurality of predetermined electrical measurements. Furthermore, the method includes applying the charge current to the battery. The method also includes detecting a plurality of subsequent electrical measurements of the battery. In addition, the method includes applying a plurality of subsequent charge currents to the battery based on the plurality of subsequent electrical measurements of the battery and the plurality of predetermined charge currents.Type: ApplicationFiled: June 26, 2012Publication date: December 26, 2013Inventors: Ripan Das, Nagasubramanian Gurumoorthy, Andy Keates
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Patent number: 8279689Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.Type: GrantFiled: May 17, 2011Date of Patent: October 2, 2012Assignee: Intel CorporationInventor: Ripan Das
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Publication number: 20110216613Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.Type: ApplicationFiled: May 17, 2011Publication date: September 8, 2011Inventor: Ripan Das
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Patent number: 7944726Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.Type: GrantFiled: September 30, 2008Date of Patent: May 17, 2011Assignee: Intel CorporationInventor: Ripan Das
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Publication number: 20100082911Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventor: Ripan Das
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Publication number: 20080162801Abstract: Series termination for a high speed interface, such as a DDR2 interface, is disclosed. In some embodiments series termination may be used instead of on-die termination to reduce power consumption on a platform.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Ripan Das, Yuancheng C. Pan, Steve Peterson