Abstract: This application provides a magneto-resistive random access memory, to reduce a chip area. The magneto-resistive random access memory includes: a plurality of stacked stacking layers, where each stacking layer includes a plurality of magnetic memory cells arranged in a two-dimensional manner; and a plurality of selective metal layers, where each stacking layer is disposed between two selective metal layers and is adjacent to the two selective metal layers, and each selective metal layer is connected to a magnetic memory cell in an adjacent stacking layer, and is configured to perform a read/write operation on the magnetic memory cell.

Abstract: An embodiment of the invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove; and forming a source and a drain in a preset source drain area along the gate length direction.

Abstract: This application provides a magneto-resistive random access memory, to reduce a chip area. The magneto-resistive random access memory includes: a plurality of stacked stacking layers, where each stacking layer includes a plurality of magnetic memory cells arranged in a two-dimensional manner; and a plurality of selective metal layers, where each stacking layer is disposed between two selective metal layers and is adjacent to the two selective metal layers, and each selective metal layer is connected to a magnetic memory cell in an adjacent stacking layer, and is configured to perform a read/write operation on the magnetic memory cell.

Abstract: An embodiment of the invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove; and forming a source and a drain in a preset source drain area along the gate length direction.

Abstract: In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally filled with a solid material, to form a filled region, and an electronic device based on the two-dimensional semiconductor is implemented by means of a doping effect of the doped region or the filled region on a characteristic of the two-dimensional semiconductor. In the embodiments of the present disclosure, doping the two-dimensional semiconductor is not directly processing the two-dimensional semiconductor. Therefore, damage caused to the two-dimensional semiconductor in a doping process and device performance deterioration caused accordingly can be effectively reduced, and stability of device performance after doping is improved.

Abstract: The invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove,; and forming a source and a drain in a preset source drain area along the gate length direction.

Abstract: The invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove,; and forming a source and a drain in a preset source drain area along the gate length direction.

Abstract: In embodiments of the present disclosure, an ambient medium of a two-dimensional semiconductor is doped or an ambient medium of a semiconductor is locally filled with a solid material, to form a filled region, and an electronic device based on the two-dimensional semiconductor is implemented by means of a doping effect of the doped region or the filled region on a characteristic of the two-dimensional semiconductor. In the embodiments of the present disclosure, doping the two-dimensional semiconductor is not directly processing the two-dimensional semiconductor. Therefore, damage caused to the two-dimensional semiconductor in a doping process and device performance deterioration caused accordingly can be effectively reduced, and stability of device performance after doping is improved.

Abstract: The invention provides a method for preparing a membrane electrode of a fuel cell, comprising the steps of preparing diffusion layers, and superimposing the diffusion layers on a proton exchange membrane having a catalyst layer on each surface, wherein the method for preparing the proton exchange membrane having a catalyst layer on each surface comprises the steps of: filling a catalyst slurry containing a catalyst and a bonding agent between two polymer films, and pressing the polymer films filled with the catalyst slurry to obtain a catalyst layer; and superimposing the catalyst layer on each surface of a proton exchange membrane. The method of the present invention can control the thickness of the catalyst layers by pressing during preparation thereof, therefore, the catalyst layers have an even thickness and surface.

Abstract: The invention provides a method for preparing a membrane electrode of a fuel cell, comprising the steps of preparing diffusion layers, and superimposing the diffusion layers on a proton exchange membrane having a catalyst layer on each surface, wherein the method for preparing the proton exchange membrane having a catalyst layer on each surface comprises the steps of: filling a catalyst slurry containing a catalyst and a bonding agent between two polymer films, and pressing the polymer films filled with the catalyst slurry to obtain a catalyst layer; and superimposing the catalyst layer on each surface of a proton exchange membrane. The method of the present invention can control the thickness of the catalyst layers by pressing during preparation thereof, therefore, the catalyst layers have an even thickness and surface.

Abstract: A sealed proton-exchange membrane fuel cell unit of this invention comprises an MEA component, a sealing unit, and current collectors for the positive and negative electrodes. The current collectors press the MEA components from each side. The MEA components comprise a proton-exchange membrane, a sealing unit, and the positive and negative electrodes attached to each side of the membrane. A sealing unit cover the edges of the proton-exchange membrane. First positioning units are located on each side of said sealing unit facing the respective current collectors of the negative and positive electrodes. At the corresponding locations on the current collectors of the negative and positive electrodes there are second positioning units. The first and second positioning units correspondingly match each other. First positioning units can be convex in shape on the surface of the sealing units.

Abstract: This invention discloses fabrication methods for membrane electrode assemblies of proton exchange membrane fuel cells, including gas diffusion electrodes. The fabrication methods of gas diffusion electrodes include the following steps: fabricating a conductive substrate; forming a layer of carbon containing material onto said conductive substrate; subjecting said conductive substrate with said carbon containing material to pressure at a predetermined temperature; cooling said conductive substrate with said material having carbon under pressure to obtain a gas diffusion layer on said conductive substrate; coating a layer of catalyst containing material onto said gas diffusion layer; subjecting said layer of catalyst containing material with gas diffusion layer and conductive substrate to pressure at another predetermined temperature; cooling under pressure to form a gas diffusion electrode.