Patents by Inventor Risa Miyazawa
Risa Miyazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11908723Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.Type: GrantFiled: December 3, 2021Date of Patent: February 20, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Akihiro Horibe, Qianwen Chen, Risa Miyazawa, Michael P. Belyansky, John Knickerbocker, Takashi Hisada
-
Publication number: 20240006371Abstract: An interconnect system may connect a first semiconductor device with second semiconductor device. The interconnect system includes patterned mask, conductive pads, solder bumps, and an adhesion layer. The patterned mask may be retained after it is utilized to fabricate the conductive pads and the solder bumps. The patterned mask may be thinned, and the adhesion layer may be formed upon the thinned patterned mask and upon the solder bumps. The adhesion layer and the solder bumps may be partially removed or planarized and the top surface of the adhesion layer that remains between the solder bumps may be coplanar with the top surface of the solder bumps.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Keiji Matsumoto, Toyohiro Aoki, Takahito Watanabe, RISA MIYAZAWA, Takashi Hisada
-
Patent number: 11735529Abstract: An integrated circuit package includes a substrate including at least one electrical connection to at least one of power or ground. The package further includes a bridge structure including at least one layer of conductive material and at least one layer of insulative material. The bridge structure is configured to be coupled to the substrate such that the conductive material is electrically connected to the at least one electrical connection. The bridge structure includes a side pad made of conductive material that is electrically connected to the at least one electrical connection. The side pad is in direct contact with the conductive material and with the insulative material of the bridge structure. The side pad forms an end face of the bridge structure such that the conductive material of the side pad is exposed.Type: GrantFiled: May 21, 2021Date of Patent: August 22, 2023Assignee: International Business Machines CorporationInventors: Takahito Watanabe, Risa Miyazawa, Hiroyuki Mori
-
Publication number: 20230178445Abstract: An electronic device is formed by dispensing an underfill material around a perimeter of an integrated circuit (IC) chip bonded to a supporting substrate. A void in present in the underfill material that is present between the IC chip and the supporting substrate. An opening is present through at least one of the IC chip and the supporting substrate into communication with the void. A vacuum may be applied to the void through the opening that is present through the IC chip to reduce a size of the void to a first volume. The opening that is present through the IC chip is sealed with a sealing plate. The underfill material is cured after the sealing of the opening to reduce of the void to at least a second volume that is less than the first volume.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventors: Toyohiro Aoki, CHINAMI MARUSHIMA, RISA MIYAZAWA, Akihiro Horibe, Takashi Hisada
-
Publication number: 20230178404Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.Type: ApplicationFiled: December 3, 2021Publication date: June 8, 2023Inventors: Akihiro Horibe, Qianwen Chen, RISA MIYAZAWA, Michael P. Belyansky, John Knickerbocker, Takashi Hisada
-
Patent number: 11574817Abstract: Aspects of the present disclosure relate to a method for fabricating an interconnection layer carrying structure. A carrier is provided. An organic layer is deposited on the carrier, wherein the organic layer includes a multi-layer wiring structure therein, and the uppermost surface is covered with an organic top layer. A sacrificial layer is deposited on the organic top layer. The carrier and the organic layer are diced together with the sacrificial layer.Type: GrantFiled: May 5, 2021Date of Patent: February 7, 2023Assignee: International Business Machines CorporationInventors: Takahito Watanabe, Risa Miyazawa, Hiroyuki Mori
-
Publication number: 20220375867Abstract: An integrated circuit package includes a substrate including at least one electrical connection to at least one of power or ground. The package further includes a bridge structure including at least one layer of conductive material and at least one layer of insulative material. The bridge structure is configured to be coupled to the substrate such that the conductive material is electrically connected to the at least one electrical connection. The bridge structure includes a side pad made of conductive material that is electrically connected to the at least one electrical connection. The side pad is in direct contact with the conductive material and with the insulative material of the bridge structure. The side pad forms an end face of the bridge structure such that the conductive material of the side pad is exposed.Type: ApplicationFiled: May 21, 2021Publication date: November 24, 2022Inventors: Takahito Watanabe, Risa Miyazawa, Hiroyuki Mori
-
Publication number: 20220359227Abstract: Aspects of the present disclosure relate to a method for fabricating an interconnection layer carrying structure. A carrier is provided. An organic layer is deposited on the carrier, wherein the organic layer includes a multi-layer wiring structure therein, and the uppermost surface is covered with an organic top layer. A sacrificial layer is deposited on the organic top layer. The carrier and the organic layer are diced together with the sacrificial layer.Type: ApplicationFiled: May 5, 2021Publication date: November 10, 2022Inventors: Takahito Watanabe, RISA MIYAZAWA, Hiroyuki Mori
-
Patent number: 11456269Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.Type: GrantFiled: March 24, 2021Date of Patent: September 27, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
-
Patent number: 11264314Abstract: An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive pads disposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.Type: GrantFiled: September 27, 2019Date of Patent: March 1, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
-
Patent number: 11164845Abstract: A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.Type: GrantFiled: January 30, 2020Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eiji Nakamura, Toyohiro Aoki, Takashi Hisada, Risa Miyazawa
-
Publication number: 20210242164Abstract: A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Inventors: Eiji Nakamura, Toyohiro Aoki, Takashi Hisada, Risa Miyazawa
-
Publication number: 20210210454Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Inventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
-
Patent number: 11004819Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.Type: GrantFiled: September 27, 2019Date of Patent: May 11, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
-
Publication number: 20210098349Abstract: An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive pads disposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
-
Publication number: 20210098404Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
-
Patent number: 10903526Abstract: A method for fabricating an electron device stack structure includes preparing plural substrates, each having a corresponding one of plural vias; sputter-depositing plural metal layers on the plural substrates to form plural electron device layers, each of the plural metal layers being sputter-deposited on a corresponding one of the plural substrates and including a part straying into a corresponding one of the plural vias as a corresponding one of plural stray metal portions; stacking the plural electron device layers to construct the electron device stack structure having a conductive path formed by connecting the plural vias; and injecting a conductive material into the conductive path to form a vertical electrical connection among the plural stray metal portions.Type: GrantFiled: November 30, 2018Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Kuniaki Sueoka, Akihiro Horibe, Risa Miyazawa
-
Publication number: 20200176821Abstract: A method for fabricating an electron device stack structure includes preparing plural substrates, each having a corresponding one of plural vias; sputter-depositing plural metal layers on the plural substrates to form plural electron device layers, each of the plural metal layers being sputter-deposited on a corresponding one of the plural substrates and including a part straying into a corresponding one of the plural vias as a corresponding one of plural stray metal portions; stacking the plural electron device layers to construct the electron device stack structure having a conductive path formed by connecting the plural vias; and injecting a conductive material into the conductive path to form a vertical electrical connection among the plural stray metal portions.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: Kuniaki Sueoka, Akihiro Horibe, Risa Miyazawa