Patents by Inventor Risaku Toda
Risaku Toda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10100858Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: GrantFiled: October 28, 2016Date of Patent: October 16, 2018Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
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Patent number: 10012568Abstract: A BiBlade sampler may include a first blade and a second blade in a retracted position. The BiBlade sampler may also include a gripper, which is driven by an actuator. The gripper may include a plurality of fingers to force the first blade and the second blade to remain in a retracted position. When the fingers are unhooked, the first blade and the second blade penetrate a surface of an object.Type: GrantFiled: July 25, 2016Date of Patent: July 3, 2018Assignee: The United States of America as Represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Paul G. Backes, Mircea Badescu, Nicholas Wiltsie, Scott J. Moreland, Jesse A. Grimes-York, Harish Manohara, Youngsam Bae, Risaku Toda, Russell G. Smith, Christopher McQuin
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Publication number: 20170045065Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: ApplicationFiled: October 28, 2016Publication date: February 16, 2017Inventors: Cecile JUNG-KUBIAK, Theodore RECK, Bertrand THOMAS, Robert H. LIN, Alejandro PERALTA, John J. GILL, Choonsup LEE, Jose V. SILES, Risaku TODA, Goutam CHATTOPADHYAY, Ken B. COOPER, Imran MEHDI
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Publication number: 20160372297Abstract: Systems and methods in accordance with embodiments of the invention generate tunable electromagnetic waves using carbon nanotube-based field emitters. In one embodiment, a CNT-based irradiator includes: at least one CNT-based cathode, itself including: a plurality of carbon nanotubes adjoined to a substrate; a plurality of anodic regions; where each anodic region is configured to emit a distinctly different class of photons in a direction away from the at least one cathode in response to a same reception of electrons; where each of the plurality of anodic regions is operable to receive electrons emitted from at least one of said at least one CNT-based cathode; and where each of the at least one CNT-based cathode and the plurality of anodic regions are disposed within a vacuum encasing.Type: ApplicationFiled: June 20, 2016Publication date: December 22, 2016Applicant: California Institute of TechnologyInventors: Harish Manohara, Risaku Toda, Mohammad M. Mojarradi, Linda Y. Del Castillo
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Patent number: 9512863Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: GrantFiled: April 26, 2013Date of Patent: December 6, 2016Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
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Patent number: 9093242Abstract: Systems and methods in accordance with embodiments of the invention proficiently produce carbon nanotube-based vacuum electronic devices. In one embodiment a method of fabricating a carbon nanotube-based vacuum electronic device includes: growing carbon nanotubes onto a substrate to form a cathode; assembling a stack that includes the cathode, an anode, and a first layer that includes an alignment slot; disposing a microsphere partially into the alignment slot during the assembling of the stack such that the microsphere protrudes from the alignment slot and can thereby separate the first layer from an adjacent layer; and encasing the stack in a vacuum sealed container.Type: GrantFiled: November 21, 2013Date of Patent: July 28, 2015Assignee: California Institute of TechnologyInventors: Harish Manohara, Risaku Toda, Linda Y. Del Castillo, Rakesh Murthy
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Patent number: 9064667Abstract: Systems and methods in accordance with embodiments of the invention implement carbon nanotube-based field emitters. In one embodiment, a method of fabricating a carbon nanotube field emitter includes: patterning a substrate with a catalyst, where the substrate has thereon disposed a diffusion barrier layer; growing a plurality of carbon nanotubes on at least a portion of the patterned catalyst; and heating the substrate to an extent where it begins to soften such that at least a portion of at least one carbon nanotube becomes enveloped by the softened substrate.Type: GrantFiled: November 15, 2013Date of Patent: June 23, 2015Assignee: California Institute of TechnologyInventors: Harish Manohara, Valerie Kristof, Risaku Toda
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Patent number: 8916394Abstract: A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.Type: GrantFiled: June 17, 2013Date of Patent: December 23, 2014Assignee: California Institute of TechnologyInventors: Risaku Toda, Michael J. Bronikowski, Edward M. Luong, Harish Manohara
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Publication number: 20140148074Abstract: Systems and methods in accordance with embodiments of the invention implement carbon nanotube-based field emitters. In one embodiment, a method of fabricating a carbon nanotube field emitter includes: patterning a substrate with a catalyst, where the substrate has thereon disposed a diffusion barrier layer; growing a plurality of carbon nanotubes on at least a portion of the patterned catalyst; and heating the substrate to an extent where it begins to soften such that at least a portion of at least one carbon nanotube becomes enveloped by the softened substrate.Type: ApplicationFiled: November 15, 2013Publication date: May 29, 2014Applicant: California Institute of TechnologyInventors: Harish Manohara, Valerie Kristof, Risaku Toda
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Publication number: 20140147192Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: ApplicationFiled: April 26, 2013Publication date: May 29, 2014Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
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Publication number: 20140141686Abstract: Systems and methods in accordance with embodiments of the invention proficiently produce carbon nanotube-based vacuum electronic devices. In one embodiment a method of fabricating a carbon nanotube-based vacuum electronic device includes: growing carbon nanotubes onto a substrate to form a cathode; assembling a stack that includes the cathode, an anode, and a first layer that includes an alignment slot; disposing a microsphere partially into the alignment slot during the assembling of the stack such that the microsphere protrudes from the alignment slot and can thereby separate the first layer from an adjacent layer; and encasing the stack in a vacuum sealed container.Type: ApplicationFiled: November 21, 2013Publication date: May 22, 2014Applicant: California Institute of TechnologyInventors: Harish Manohara, Risaku Toda, Linda Y. Del Castillo, Rakesh Murthy
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Publication number: 20130302633Abstract: A micro-scaled bi-material lattice structure includes a frame comprising a first material having a first coefficient of expansion and defining a plurality of unit cells. The bi-material lattice structure further includes a plurality of plates comprising a second material having a second coefficient of expansion different from the first coefficient of expansion. One of the plates is connected to each unit cell. The bi-material lattice structure has a third coefficient of expansion different from both the first coefficient of the expansion and the second coefficient of expansion, and the bi-material lattice structure has a thickness of about 100 nm to about 3000 microns.Type: ApplicationFiled: April 17, 2013Publication date: November 14, 2013Inventors: Sergio Pellegrino, Keith D. Patterson, Chiara Daraio, Eleftherios Gdoutos, Namiko Yamamoto, Risaku Toda, Victor E. White, Harish Manohara, John B. Steeves
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Publication number: 20130301113Abstract: A deformable mirror is configured to be deformed by surface-parallel actuation. In one embodiment, the deformable mirror includes a first piezoelectric active layer on a first surface of a substrate. The first piezoelectric active layer has a substantially uniform thickness across the first surface of the substrate. The mirror also includes a first electrode layer on the first piezoelectric active layer. The first electrode layer has a plurality of electrodes arranged in a first pattern and has a substantially uniform thickness across the first piezoelectric active layer. The mirror may further include a second piezoelectric layer on the first electrode layer, and a second electrode layer on the second piezoelectric layer. The electrodes of the first and second electrode layers are configured to supply a voltage to the piezoelectric active layers upon actuation to thereby locally deform the shape of the mirror to correct for optical aberrations.Type: ApplicationFiled: April 17, 2013Publication date: November 14, 2013Inventors: Sergio Pellegrino, Keith D. Patterson, Chiara Daraio, Eleftherios Gdoutos, Namiko Yamamoto, Risaku Toda, Victor E. White, Harish Manohara, John B. Steeves
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Publication number: 20130280830Abstract: A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.Type: ApplicationFiled: June 17, 2013Publication date: October 24, 2013Inventors: Risaku TODA, Michael J. BRONIKOWSKI, Edward M. LUONG, Harish MANOHARA
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Publication number: 20110057164Abstract: A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.Type: ApplicationFiled: June 17, 2008Publication date: March 10, 2011Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Risaku Toda, Michael J. Bronikowski, Edward M. Luong, Harish Manohara
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Publication number: 20030150268Abstract: A system and method for reducing electric discharge breakdown occurrences in a micro-electromechanical system device is provided. The device comprises a core, a shell, and electrodes, which may be formed on the shell. When voltage is applied to the electrodes, each electrode applies an electrostatic force on the core. The electrodes are arranged in concentric sets, where each set may comprises two or more electrodes. Due to the concentricity of the electrodes, a minimum distance is maintained between the core and an outer electrode of an electrode set when the core nears or touches an inner electrode of the electrode set.Type: ApplicationFiled: February 8, 2002Publication date: August 14, 2003Applicant: Ball Semiconductor, Inc.Inventors: Nobuo Takeda, Risaku Toda
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Patent number: 6505409Abstract: An inclinometer comprising a spherical mass, a spherical shell having a reference axis and surrounding said spherical mass and a plurality of electrodes mounted on the spherical inner surface of said spherical shell, said inclinometer applied to detect the inclination angle of said reference axis by the output signal of said electrodes.Type: GrantFiled: November 30, 1999Date of Patent: January 14, 2003Assignee: Ball Semiconductor, Inc.Inventors: Risaku Toda, Masayoshi Esashi
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Publication number: 20020132113Abstract: A method for coating a micro-electromechanical system (MEMS) device is provided. A coating material, such as a ceramic slurry, may be utilized to form a gas permeable enclosure or shell around the device after the coating material hardens. A vacuum may be applied near the device to exert an attractive force on the coating material to aid in homogenously distributing the coating material over the device. In addition, a vibration may be applied to the device to aid in distributing the coating material. If the device is attached to a substrate, a hole may be formed through the substrate with one opening near the device and a second opening located elsewhere. The vacuum may then be applied to the second opening to draw the coating material over the device and towards the first opening.Type: ApplicationFiled: January 18, 2002Publication date: September 19, 2002Applicant: Ball Semiconductor, Inc.Inventors: Tomoki Tanaka, Risaku Toda
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Patent number: 6444135Abstract: A method and system for making a gas permeable shell in a micro electromechanical systems (MEMS) device is disclosed. The MEMS device is created with an internal sacrificial layer. The device is then coated with a slurry composition which, after drying, is later exposed to a solvent. As a result, the sacrificial layer is removed to produce interconnected voids.Type: GrantFiled: October 16, 2000Date of Patent: September 3, 2002Assignee: Ball Semiconductor, Inc.Inventors: Murali Hanabe, Risaku Toda
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Patent number: 6440253Abstract: A method and system for securing a small spherical shaped semiconductor substrate for processing operations, such as lithography, is disclosed. The substrate is secured by attaching it to a member and applying an adhering substance, such as photo resist, to the substrate and a portion of the member. The application may be by electroplating or other means. The electroplated substance securely attaches the substrate to the member so that one or more processing operations may be performed on the substrate. After processing, the substrate can be removed from the member.Type: GrantFiled: February 14, 2000Date of Patent: August 27, 2002Assignee: Ball Semiconductor, Inc.Inventor: Risaku Toda