Abstract: A system includes a first memory device; a second memory device; and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including: allocating a first portion of the second memory device to a first namespace of a plurality of namespaces of the second memory device and allocating a first portion of the first memory device to a first address mapping data structure for storing metadata of the first namespace. A size of the first address mapping data structure is calculated using a first address mapping granularity level of the first address mapping data structure and a capacity of the first portion of the second memory device. The operations further include allocating a second portion of the second memory device to a second namespace of the plurality of namespaces of the second memory device and allocating a second portion of the first memory device to a second address mapping data structure for storing metadata of the second namespace.

Abstract: Implementations herein relate to memory system repair operations. In some implementations, the memory system may include a memory bank, remapping circuitry, and a nonvolatile memory array. The memory bank may include a set of rows (e.g., that are addressable by a host system) and one or more spare rows that are configured to replace defective rows by performing repair operations on the defective rows. The remapping circuitry may be configured to update a mapping of addresses from defective rows to the spare rows, and the nonvolatile memory array may be configured to store physical addresses of the defective rows based on performing repair operations on the defective rows. In some cases, the memory system may identify the spare rows and the updated mapping of the addresses during an initialization operation of the memory system based on the nonvolatile memory array storing the physical addresses of the defective rows.

Abstract: Methods, systems, and devices for using unreliable memory dies for access operations are described. A memory system may include one or more ranks that each include a plurality of memory dies that are connected to a common chip select. When accessing the memory system, data may be read from or written to a codeword that includes memory cells from multiple (e.g., two) ranks. In some instances, the size of data read from and written to the memory system may be such that some ranks may not need to be fully populated (e.g., a rank could include fewer memory dies than other ranks). Because the memory dies may not be individually accessible, the memory system may fully populate some ranks using less reliable or otherwise defective memory dies whose logic and I/Os are functional.

Abstract: In some implementations, a memory apparatus may receive a command to write data to volatile memory of the memory system. The memory apparatus may compare the data to one or more data patterns to identify whether the data matches a data pattern of the one or more data patterns. The memory apparatus may increment a reference counter associated with the data pattern based on identifying that the data matches the data pattern. The memory apparatus may write, based on identifying that a measure flag associated with the data pattern is set, the data to the volatile memory.

Abstract: Implementations herein relate to a memory system with a dynamic capacity. In some implementations, the memory system may include a set of memory arrays that corresponds to a first address space and that includes a plurality of disjoint subsets of memory arrays. Additionally, the first address space may be divided into a plurality of capacity blocks that are each associated with a respective one of the plurality of disjoint subsets. The memory system may additionally include error detection circuitry configured to detect an error in a memory array within a first disjoint subset and a controller configured to remap a portion of the plurality of capacity blocks to a second address space, where the second address space does not include a first capacity block based on the first capacity block being associated with the first disjoint subset including the error.

Abstract: A memory device includes a memory cache to store write data comprising a plurality of data segments; a pattern database configured to store one or more data patterns; a deduplication engine configured to: identify whether a pattern of a data segment matches any data pattern, based on the pattern of the data segment matching any data pattern, identify the data segment as a duplicated data segment, remove the duplicated data segment from the write data to generate deduplicated write data, identify a pattern reference corresponding to a matching pattern that matches the pattern of the data segment, and generate a deduplication information including the pattern reference; a compression engine configured to compress the deduplication information and the deduplicated write data; and a memory array configured to store compressed deduplication information and compressed deduplicated write data.

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

Abstract: A method for compressing data in a memory device involves receiving write data, splitting the write data into sub-blocks based on a compression block size, and compressing each sub-block to produce compressed sub-blocks. The method includes writing the compressed sub-blocks into a write block of memory cells, where at least one compressed sub-block spans multiple sub-blocks, and adding padding only at the end of the write block. An indirection table manages the mapping of compressed sub-blocks within the write block, with entries indicating the start of each write block and the location of each compressed sub-block. The method also includes retrieving specific data blocks using the indirection table and adapting the indirection block size based on data compression entropy to optimize memory space and performance.

Abstract: A system includes a first memory device; a second memory device; and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including: determining a size of the first memory device designated for storing a plurality of address mapping data structures, wherein each address mapping data structure of the plurality of address mapping data structures is associated with a corresponding namespace of a plurality of namespaces, wherein each namespace of the plurality of namespaces is associated with a corresponding region of a second memory device; associating a first address mapping granularity level with the first memory device for storing a first address mapping data structure of the plurality of address mapping data structures; determining a remaining available space of the first memory device by excluding a first size of the first address mapping data structure from the size of the first memory device, wherein the first size is calculated based on

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Abstract: In some implementations, a memory apparatus may receive a command to write data to volatile memory of the memory system. The memory apparatus may compare the data to one or more data patterns to identify whether the data matches a data pattern of the one or more data patterns. The memory apparatus may increment a reference counter associated with the data pattern based on identifying that the data matches the data pattern. The memory apparatus may write, based on identifying that a measure flag associated with the data pattern is set, the data to the volatile memory.

Abstract: A system may include memory including memory blocks and a memory device processor configured to dynamically allocate the memory blocks in different RAS (Reliability, Availability and Serviceability) modes that have different power and reliability characteristics. The memory device processor may be configured to dynamically allocate a first of the memory blocks in a first RAS mode and dynamically allocate a second of the memory blocks in a second RAS mode. Benefits include flexibility in allocating memory for different uses to appropriately balance performance and reliability and thus improve overall system performance.

Abstract: A system includes a first memory device; a second memory device; and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including: determining a size of the first memory device designated for storing a plurality of address mapping data structures, wherein each address mapping data structure of the plurality of address mapping data structures is associated with a corresponding namespace of a plurality of namespaces, wherein each namespace of the plurality of namespaces is associated with a corresponding region of a second memory device; associating a first address mapping granularity level with the first memory device for storing a first address mapping data structure of the plurality of address mapping data structures; determining a remaining available space of the first memory device by excluding a first size of the first address mapping data structure from the size of the first memory device, wherein the first size is calculated based on

Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.

Abstract: A system including a memory device and an operatively coupled processing device to perform operations determining a size of a minimum allocation unit (MAU) for a plurality of logical devices, dividing the memory device into logical units with a size equal to the MAU, identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device, identifying, using a logical unit identifier (LUI) data structure, a first set of LUI that are available, wherein the first set of LUI identify a first set of logical units, allocating the first set of logical units to the first logical device, and updating an LDI-to-LUI mapping data structure to reflect that the first set of logical units are allocated to the first logical device.

Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

Abstract: A variety of applications can include a memory device implementing a dual compression scheme. A memory subsystem of the memory device can be arranged into multiple regions. A first region of the memory subsystem can be used to store non-compressible data. A second region can be used to store compressible data. The second region can have a first subregion and a second subregion. The first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. The second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.

Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.