Abstract: Techniques are provided for configuring and operating hardware to sustain real-time hashing throughput. In an embodiment, during a first set of clock cycles, a particular amount of data items of a first data column are transferred into multiple hash lanes. During a second set of clock cycles, the same particular amount of data items of a second data column are transferred into the hash lanes. The transferred data items of the first and second data columns are then processed to calculate a set of hash values. When combined with techniques such as pipelining and horizontal scaling, the loading, hashing, and other processing occur in real time at the full speed of the underlying data path. For example, hashing throughput may sustainably equal or exceed the throughput of main memory.

Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.

Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.

Abstract: A multilayer flexible film for packaging a transdermal patch product comprising a pharmaceutical active agent comprises: a product-contacting sealing layer comprising a co-polyester having a surface energy of at least 50 dyne/cm2; and one or more layers above the product-contacting sealing layer. The pharmaceutical active agent may comprise nicotine. An average adhesion force to peel the transdermal patch from the product-contacting sealing layer may be less than 100 g/inch (39.37 g/cm).

Abstract: The present disclosure describes a method for cloud resource placement optimization. A resources monitor monitors state information associated with cloud resources and physical hosts in the federated cloud having a plurality of clouds managed by a plurality of cloud providers. A rebalance trigger triggers a rebalancing request to initiate cloud resource placement optimization based on one or more conditions. A cloud resource placement optimizer determines an optimized placement of cloud resources on physical hosts across the plurality of clouds in the federated cloud based on (1) costs including migration costs, (2) the state information, and (3) constraints, wherein each physical host is identified in the constraints-driven optimization solver by an identifier of a respective cloud provider and an identifier of the physical host. A migrations enforcer determines an ordered migration plan and transmits requests to place or migrate cloud resources according to the ordered migration plan.

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Abstract: Improved sensor assemblies are provided. More particularly, the present disclosure provides improved and highly advantageous metal oxide based sensor assemblies configured to sense low concentration of specific gases, and related methods of use. The present disclosure provides improved physical forms of metal oxide films (e.g., WOx films, CeOx films). The exemplary metal oxide films can be fabricated by a Reactive Spray Deposition Technology (RSDT). The highly advantageous films/materials can be utilized in sensor assemblies to detect simple chemical components of the breath that correlate with human health conditions (e.g., the presence of acetone in diabetic patients). These films/materials demonstrate improved thermal stability under the sensor's operating conditions, as well as improved sensitivity to low concentration of the analyte, selectivity and quick responsiveness.

Abstract: Techniques are provided for improving the performance of a constellation of coprocessors by hardware support for asynchronous events. In an embodiment, a coprocessor receives an event descriptor that identifies an event and a logic. The coprocessor processes the event descriptor to configure the coprocessor to detect whether the event has been received. Eventually a device, such as a CPU or another coprocessor, sends the event. The coprocessor detects that it has received the event. In response to detecting the event, the coprocessor performs the logic.

Abstract: Transaction requests may be ordered in a distributed database according to an independently assigned sequence. Different distributed system nodes, such as a transaction coordinator and a storage node may independently assign sequence numbers to requests to access a distributed database. A storage node may receive the request from a transaction coordinator with an assigned sequence number and another request to which the storage node may assign a sequence number. The storage node can then order performance of the requests based on the sequence numbers.

Abstract: Improved sensor assemblies are provided. More particularly, the present disclosure provides improved and highly advantageous metal oxide based sensor assemblies configured to sense low concentration of specific gases, and related methods of use. The present disclosure provides improved physical forms of metal oxide films (e.g., WOx films, CeOx films). The exemplary metal oxide films can be fabricated by a Reactive Spray Deposition Technology (RSDT). The highly advantageous films/materials can be utilized in sensor assemblies to detect simple chemical components of the breath that correlate with human health conditions (e.g., the presence of acetone in diabetic patients). These films/materials demonstrate improved thermal stability under the sensor's operating conditions, as well as improved sensitivity to low concentration of the analyte, selectivity and quick responsiveness.

Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.

Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Abstract: The present disclosure describes a method for cloud resource placement optimization. A resources monitor monitors state information associated with cloud resources and physical hosts in the federated cloud having a plurality of clouds managed by a plurality of cloud providers. A rebalance trigger triggers a rebalancing request to initiate cloud resource placement optimization based on one or more conditions. A cloud resource placement optimizer determines an optimized placement of cloud resources on physical hosts across the plurality of clouds in the federated cloud based on (1) costs including migration costs, (2) the state information, and (3) constraints, wherein each physical host is identified in the constraints-driven optimization solver by an identifier of a respective cloud provider and an identifier of the physical host. A migrations enforcer determines an ordered migration plan and transmits requests to place or migrate cloud resources according to the ordered migration plan.

Abstract: The present disclosure describes a method for cloud resource placement optimization. A resources monitor monitors state information associated with cloud resources and physical hosts in the federated cloud having a plurality of clouds managed by a plurality of cloud providers. A rebalance trigger triggers a rebalancing request to initiate cloud resource placement optimization based on one or more conditions. A cloud resource placement optimizer determines an optimized placement of cloud resources on physical hosts across the plurality of clouds in the federated cloud based on (1) costs including migration costs, (2) the state information, and (3) constraints, wherein each physical host is identified in the constraints-driven optimization solver by an identifier of a respective cloud provider and an identifier of the physical host. A migrations enforcer determines an ordered migration plan and transmits requests to place or migrate cloud resources according to the ordered migration plan.

Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.

Abstract: A film for packaging a pharmaceutical active agent-containing product includes a product-contacting sealing layer that does not scalp the pharmaceutical active product. The product contacting layer includes at least 90 wt. % of a CTFE-VDF copolymer. The pharmaceutical active agent can be nicotine. The product can be a transdermal patch.

Abstract: The present invention relates to methods and devices for characterizing wounds, and in particular to the use of Raman spectroscopy to characterize the state of healing of a wound.

Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.